HDLBits经典题目分享-笔者的做题思路与收获

前言：

笔者将在这个文章下更新一些HDLBits的经典题目,仅供大家参考,题号将和HDLBits保持一致,关于题目的翻译仅是笔者自己的理解,可能会造成错误,望谅解,笔者会根据每天刷的题目同步更新

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2.2.2 Vectors in more detail（更详细的向量）

问题描述

Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.

构建一个组合电路，将输入半字（16位[15:0]）拆分为低位[7:0]和高位[15:8]字节。

Verilog代码

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    assign out_hi = in[15:8];
    assign out_lo = in[7:0]; 
//另一种方法
//assign {out_hi, out_lo} = in;

endmodule

2.2.3 vector part select (反转向量)

问题描述

Build a circuit that will reverse the byte ordering of the 4-byte word.

颠倒四字节字的字节顺序

Verilog代码

module top_module( 
    input [31:0] in,
    output [31:0] out );//
    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];
    

    // assign out[31:24] = ...;

endmodule

2.2.4 Bitwise operators (位操作)

问题描述

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

有两个三位的输入a.b,两个三位的输出out_or_bitwise,out_or_logical,一个6位的输出out_not,其中out_or_bitwise为a,b的位或.out_or_logical为a,b的逻辑或,out_not为a,b的取反预算,其中高3位为b,第三位为a

Verilog代码

这是笔者的代码

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = ~(~a&~b);
    assign out_or_logical = a||b;
    assign out_not[5:3]= ~b;
    assign out_not[2:0]= ~a;
    

endmodule

这是官方回答

module top_module(
	input [2:0] a, 
	input [2:0] b, 
	output [2:0] out_or_bitwise,
	output out_or_logical,
	output [5:0] out_not
);
	
	assign out_or_bitwise = a | b;
	assign out_or_logical = a || b;

	assign out_not[2:0] = ~a;	// Part-select on left side is o.
	assign out_not[5:3] = ~b;	//Assigning to [5:3] does not conflict with [2:0]
	
endmodule

原来"|“是按位或,”||"是逻辑或

2.2.5 Four Input Gate (四输入门)

问题描述

Build a combinational circuit with four inputs, in[3:0].
构建一个有四输入的组合电路

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;

endmodule

异或的符号是^

2.2.6 Vector concatenation operator (向量拼接运算符)

问题描述

Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:

把6个5位a,b,c,d,e,f拼接成一个4个8位的w,x,y,z,最末位是11

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    // assign { ... } = { ... };
    assign w = {a[4:0],b[4:2]};
    assign x = {b[1:0],c[4:0],d[4]};
    assign y = {d[3:0],e[4:1]};
    assign z = {e[0],f[4:0],2'b11};

endmodule

需要注意的是:
后面那两位11应该用2’b11否则会报错

2.2.7 Vector reversal (向量反转)

问题描述

Given an 8-bit input vector [7:0], reverse its bit ordering.

反转一个8位向量

笔者代码

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out [7] = in [0];
    assign out [6] = in [1];
    assign out [5] = in [2];
    assign out [4] = in [3];
    assign out [3] = in [4];
    assign out [2] = in [5];
    assign out [1] = in [6];
    assign out [0] = in [7];

    
endmodule

官方代码

module top_module (
	input [7:0] in,
	output [7:0] out
);
	
	assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule

差不多就按照这个类型写

2.2.8 Replication operator (重复拼接)

问题描述

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

输出是32位的out,输入是8位的in,需要将in的第8位复制24次,后面接上in,拼接为out

代码

module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out[31:0] = {{24{in[7]}},in};

endmodule

2.2.8 More Replication (更多拼接)

问题描述

As the diagram shows, this can be done more easily using the replication and concatenation operators.
The top vector is a concatenation of 5 repeats of each input
The bottom vector is 5 repeats of a concatenation of the 5 inputs

有五个一位的输入,a,b,c,d,e,将a,b,c,d,e重复和拼接进行同或运算

抄的答案

module top_module (
	input a, b, c, d, e,
	output [24:0] out
);
 
	wire [24:0] top, bottom;
	assign top    = { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} };
	assign bottom = {5{a,b,c,d,e}};
	assign out = ~top ^ bottom;	// Bitwise XNOR
 
	// This could be done on one line:
	// assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
	
endmodule

同或符号:~top ^ bottom

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