HDLBits练习记录---Vectors

1.bitwise-OR、logical-OR、inverse (NOT)

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    assign out_or_bitwise[2:0] = a[2:0] | b[2:0];
    assign out_or_logical = a[2:0] || b[2:0];
    assign out_not[5:3] = ~b[2:0];
    assign out_not[2:0] = ~a[2:0];
    
endmodule

2.four inputs gates

3.vector the concatenation operator

4.Vector reversal 1

5.Replication operator

6.More replication

xor(异或门，相异为1） / xnor（同或门，相同为1）