verilog实现8位通用移位寄存器的设计，modelsim输出波形

本实验要求设计一个模式可控的移位寄存器，该寄存器可以对 8 位信号通过 MD 输入端控制移位输出的模式，其功能表如表 所示。

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移位寄存器功能表

CLK	MD	状态
↑	001	带进位循环左移
↑	010	带进位循环右移
↑	011	自循环左移
↑	100	自循环右移
↑	101	加载待移数据
↑	其他	保持

module shift_register(
	input clk,
	input [2:0]MD,
	input [7:0]data_in,
	input carry_in,
	output reg[7:0]shift_reg,
	output reg[7:0]data_out	
);

always @(posedge clk)begin
	
	case(MD)
	3'b001:begin
	
	data_out = {data_in[6:0],carry_in};
	shift_reg = data_out;
	end
	3'b010:begin
	
	data_out = {carry_in,data_out[7:1]};
	shift_reg = data_out;
	end
	3'b011:begin
	data_out = {data_out[6:0],data_out[7]};
	shift_reg = data_out;
	end
	3'b100:begin
	
	data_out = {data_out[0],data_out[7:1]};
	shift_reg = data_out;
	end
	3'b101:begin
	data_out = data_in;
	shift_reg = data_out;	
	end
	default:begin
	data_out = data_out;

	end
   endcase	
end


endmodule

测试文件

`timescale 1ns/1ps

module shift_register_tb;

	reg clk;
	reg[2:0]MD;
	reg[7:0]data_in;
	reg carry_in;
	
	wire[7:0]data_out;
	wire[7:0]shift_reg;
	
	shift_register uut(
	.clk(clk),
	.MD(MD),
	.data_in(data_in),
	.data_out(data_out),
	.carry_in(carry_in),
	.shift_reg(shift_reg)
	);
	
	always#10 clk = ~clk;
	
	initial begin
	clk = 0;
	MD = 3'b000;
	data_in = 8'b00000000;
	carry_in = 1'b0;
	
	#20
	MD = 3'b001;
	carry_in = 1'b1;
	#20;
	
	MD = 3'b010;
	carry_in = 1'b1;
	#20;
	
	MD = 3'b011;
	
	#20;

	MD = 3'b100;
	#20
	
	MD = 3'b101;
	data_in = 8'b00001111;
	#20;

	MD = 3'b100;
	carry_in = 1'b0;
	#20;
	
	end
endmodule