快心梗了,这个题写了三个小时还是报错,哪个好心人能不能给我看看!!!
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter left=0,right=1,dl=2,dr=3,digl=4,digr=5,sl=6,sr=7;
reg [4:0] q;
reg [2:0] state,nstate;
initial
q=1;
always@(posedge clk or posedge areset)
begin if(areset)
q<=1;
else if(!ground)
q<=q+1'b1;
else
q<=1;
end
always@(*)
begin
case(state)
left:nstate=(~ground?dl:(dig?digl:(bump_left?right:left)));
right:nstate=(~ground?dr:(dig?digr:(bump_right?left:right)));
dl:begin
if(!ground)
nstate=dl;
else if(q>20&&ground)
nstate=sl;
else if(q<=20&&ground)
nstate=left;
end
dr:begin
if(!ground)
nstate=dr;
else if(q>20&&ground)
nstate=sr;
else if(q<=20&&ground)
nstate=right;
end
digl:nstate=(ground?digl:dl);
digr:nstate=(ground?digr:dr);
sl:nstate=sl;
sr:nstate=sr;
endcase
end
always@(posedge clk or posedge areset)
begin
if(areset)
state<=left;
else
state<=nstate;
end
assign walk_left=(state==sl||state==sr)? 0:(state==left);
assign walk_right=(state==sl||state==sr)? 0:(state==right);
assign aaah=(state==sl||state==sr)? 0:(state==dr||state==dl);
assign digging=(state==sl||state==sr)? 0:(state==digl||state==digr);
endmodule