4分频 分频器

module divider_4(
input external_clk;
input reset;

output divider_clk;
);

reg divider_clk, counter;

always@(posedge external_clk or negedge external_clk)begin
    if(!reset)
        counter <= 2'd0;
    else if(cnt == 2'd1)
         counter <= 2'd0;
    else
        counter <= counter + 2'd1;
end

always@(posedge external_clk or negedge external_clk)begin
    if(!reset)
        divider_clk <= 2'd0;
    else if(cnt == 2'd1)
         divider_clk <= ~divider_clk;
    else
        ;
end

endmodule