module edge_capture(
input sys_clk,
input sys_rst_n,
input text,
output posedge_edge,
output negedge_edge,
output edge_all
);
reg text_delay;
always@(posedge sys_clk or negedge sys_clk)begin
if(!sys_rst_n)
text_delay <= 1'b0;
else
text_delay <= text;
end
assign posedge_edge = text & ~text_delay;
assign negedge_edge = ~text & text_delay;
assign edge_all = text ^ text_delay;
endmodule
边沿检测设计
最新推荐文章于 2024-07-16 11:17:57 发布