VMM验证方法学学习随笔

1，计分板（scoreboard)

  记分板用来动态预测设计的响应，施加给DUT的激励同时施加给记分板，记分板中的转换函数把输入的激励全部转换成最后响应的形式，并保存在数据结构中，以传递给检查器，记分板还对所有的事务进行纪录与统计，记录执行的事务个数，成功失败的事务个数，是否某一事务被遗漏等。

2，场景（scenario)

场景(Scenario)，主要是用来生成具有一定关系的随机事务的序列。

3，基本类，最常用的大致有如下这9个basic class:

vmm_env，vmm_xactor，vmm_channel，vmm_data，vmm_log，vmm_atomic_gen，

vmm_scenario_gen，vmm_notify，vmm_test。

 

VMM验证方法学，主要由一些基本类来构成验证方法学的验证环境，其中几个必须掌握的基本类如下：

  vmm_data：非常重要的基本类，很多其他的类是由其引申和扩展而来；

  vmm_xactor: 非常中移动基本类，应用场合非常多，其他很多的基本类是由其引申和扩展而来。

vmm_data和vmm_xactor是学习VMM验证方法学的重点也是难点，务必理解透彻。

 

VMM方法学通过 4个不同的机制来提高项目验证的生产率。这四个机制为别为 :断言、抽象化、自动化和重用。

In this section you will find explanation of vmm base classes and architecture of the vmm based testbench.

vmm basic classes:

Index :
        -- VMM log : Vmm log message example, macros, severity and method
        -- VMM Data : VMM data class is used to model transaction, packet or item
        -- VMM channel : Vmm channel is a inferface to connect the generators and transactors to pass the transaction object
        -- VMM Xactor : All the running components like transactor, generator, monitor, scoreboard etc are deriverd from xactor class
        -- VMM notify : VMM notify base class
        -- VMM Atomic Gen : VMM atomic generator is used to generate the transaction randomly
        -- VMM env : Verfication environments should be extened from vmm_env class
        -- VMM Callbacks : Callbacks are used to change the behavior of a verification component without actually changing the compoent

 

vcs常用命令使用详解

+v2k
Enables language features in the IEEE 1364-2001 standard.

success报告成功匹配
Enables reporting of successful matches, and successes on
cover statements, in addition to failures. The default is to report
only failures.


filter过滤掉空成功。
Blocks reporting of trivial implication successes. These happen
when an implication construct registers a success only because
the precondition (antecedent) portion is false (and so the
consequent portion is not checked). With this option, reporting
only shows successes in which the whole expression matches.


-assert filter+success经常两者结合起来用。注意用时在filter+success前加上-assert

maxsuccess=N
Limits the total number of reported successes to N. You must
supply N, otherwise no limit is set. VCS continues to monitor
assertions even after the limit is reached.

-assert maxsuccess=3

-l filename logfile文件名
Specifies a file where VCS records compilation messages. If you
also enter the -R or -RI option, VCS records messages from both
compilation and simulation in the same file.


-assert enable_diag
Enables further control of results reporting with runtime options

-sverilog
Enables the use of SystemVerilog code.

-cm assert
Compiles for SystemVerilog assertions coverage. -cm is not a
new compile-time option but the assert argument is new. This
option and argument must also be entered at runtime.



vcs *.v *.sva -sverilog \
+define+enable_blk_assertions \
+define+tb_sva \
+define+slv_fc \
+define+slv_doc \
-PP -assert enable_diag -cm assert \
-l compile.log


simv -l run.log -assert filter+success -assert maxsuccess=3

VCS对verilog模型进行仿真包括两个步骤:
  1. 编译verilog文件成为一个可执行的二进制文件命令为:
    {1}gt; vcs source_files

  2. 运行该可执行文件
    {1}gt; ./simv
 
  类似于NC, 也有单命令行的方式:
    {1}gt; vcs source_files -R
    -R 命令表示, 编译后立即执行.
    
    
-cm line|cond|fsm|tgl|obc|path     设定coverage的方式


A few more compile options are significant:
1.  if RVM class libs are used in the OV code, this is required:
-ntb_opts rvm
2. VMM classes, vmm_ macros can be used in SV; and rvm_ macros
in OV package are automatically translated to vmm_ equivalents if
this is also added
-ntb_opts interop -ntb_opts rvm

-lca
这是VCS的参数，表示使用VCS的“用户限制使用”的功能，即VCS提供的一些功能是他们还没有经过充分测试还没有发布的；如果你想使用这些功能就要加上 -lca参数。

+incdir+directory
Specifies the directory or directories that VCS searches for include
files used in the `include compiler directive. More than one
directory may be specified, separated by +.

+plusarg_save
Some runtime options must be preceded by the +plusarg_save
option for VCS to compile them into the executable. You can
specify this option either on the vcs command line or in the file
specified with the -f or -F option.
You can also enter the following runtime options on the vcs command
line or in the file that you specify with the -f or -F compile-time option,
so that VCS compiles them into the simv executable, BUT you must
precede them with the +plusarg_save compile-time option:
+cfgfile +override_model_delays
+vcs+dumpoff +vcs+dumpon
+vcs+dumpvarsoff +vcs+grwavesoff
+vcs+ignorestop +vcs+learn+pli
+vcs+mipd+noalias +vcs+nostdout
+vcs+stop +vera_load
+vera_mload +vpdbufsize
+vpddrivers +vpdfile
+vpdfilesize +vpdnocompress
+vpdnostrengths +vpdports
+vpdupdate

-ntb_opts dtm
You enable testbench constructs outside programs with the
-ntb_opts dtm compile-time option and keyword argument.
The testbench constructs that you can enter outside programs with
this option are as follows:classes   associative arrays   dynamic arrays   
SystemVerilog named events

 

工作状态: 建立仿真环境
 
  VCS是Synopsys公司的仿真工具.

  VCS对verilog模型进行仿真包括两个步骤:
  1. 编译verilog文件成为一个可执行的二进制文件命令为:
    >vcssourcefiles2.运行该可执行文件>vcssourcefiles2.运行该可执行文件> ./simv
 
  类似于NC, 也有单命令行的方式:
    $> vcs source_files -R
    -R 命令表示, 编译后立即执行.

    下面讲述常用的命令选项:
  -cm line|cond|fsm|tgl|obc|path     设定coverage的方式
 
  +define+macro=value+       预编译宏定义

  -f filename             RTL文件列表

  +incdir+directory+           添加include 文件夹

  -I                 进入交互界面

  -l                 logfile文件名

  -P pli.tab             定义PLI的列表(Tab)文件

  +v2k                 使用推荐的标准

  -y                 定义verilog的库

  -notice               显示详尽的诊断信息

  -o                 指定输出的可执行文件的名字,缺省是sim.v

 

 

interface:

注意，interface是DUT和testbench的接口。故interface不能简单的将DUT的顶层设计的端口信号复制过来了事。由于interface是DUT和testbench的接口，故其端口方向与DUT的顶层设计的端口信号的方向不同。

 

assertion:

需要注意，assertion是嵌入到设计内部去的，所以assertion模块的端口信号列表的信号，对于assertion本身来讲，都是熟人信号。不能按照设计的端口信号列表的信号方向来定义，否则将会出现编译问题。如：

variable driven by a stuctural diver cannot have any other drivers.