STM32 MPU 阅读笔记

MPU简介

MPU 可以将 memory map 内存映射区分为多个具有一定访问规则的区域，通过这些规则可以实现

如下功能：

• 防止不受信任的应用程序访问受保护的内存区域。

• 防止用户应用程序破坏操作系统使用的数据。

• 通过阻止任务访问其它任务的数据区。

• 允许将内存区域定义为只读，以便保护重要数据。

• 检测意外的内存访问。

内存映射就是 32 位的 CM7 内核整体可以寻址的 0 到 2^32 -1 共计 4GB 的寻址空间。通过这些地址可以访 问 RAM、Flash、外设等。下面是内存映射的轮廓图，IC 厂家使用时，再做细分，添加相应的硬件功能。

MPU的功能实现

MPU 可以配置保护 16 个内存区域（这 16 个内存域是独立配置的），每个区域最小要求 256 字节，每个区域还可以配置为 8 个子区域。由于子区域一般都相同大小，这样每个子区域的大小就是 32 字节，正好跟 Cache 的 Cache Line 大小一样。

MPU 可以配置的 16 个内存区的序号范围是 0 到 15，还有默认区 default region，也叫作背景区，序号 -1。由于这些内存区可以嵌套和重叠，所以这些区域在嵌套或者重叠的时候有个优先级的问题。序号 15 的优先级最高，以此递减，序号 -1，即背景区的优先级最低。这些优先级是固定的。

下面通过一个具体的实例帮助大家理解。如下所示共有 7 个区，背景区和序号 0-5 的区。内存区 4 跟内存区 0 和 1 有重叠部分，那么重叠部分将按照内存区 4 的配置规则执行；内存区 5 被完全包含在内存区 3 里面，那么这部分内存区将按照内存区 5 的配置规则执行。

MPU 可以配置的三种内存类型

MPU 可以配置的三种内存类型如下：

• Normal memory

  CPU 以最高效的方式加载和存储字节、半字和字，对于这种内存区，CPU 的加载或存储不一定要按照程序列出的顺序执行。

• Device memory

  对于这种类型的内存区，加载和存储要严格按照次序进行，这样是为了确保寄存器按照正确顺序设置。

• Strongly ordered memory

  程序完全按照代码顺序执行，CPU 需要等待当前的加载/存储指令执行完毕后才执行下一条指令。这样会导致性能下降。

MPU 的内存属性

Use the MPU registers to define the MPU regions and their attributes.

MPU 相关寄存器

MPU type register

The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. If the MPU is not present the MPU_TYPE register is RAZ.

MPU_TYPE 寄存器指示 MPU 是否存在，如果存在，指示它支持多少个区域。如果 MPU 不存在，则 MPU_TYPE 寄存器为 RAZ。

MPU control register

The MPU_CTRL register:

• Enables the MPU.

• Enables the default memory map background region.

• Enables use of the MPU when in the hard fault, Non Maskable Interrupt (NMI), and FAULTMASK escalated handlers.

MPU region number register

The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers.

Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.

REGION：The MPU supports 8 or 16 memory regions, so the permitted values of this field are 0-7 or 0-15.

MPU region base address register

The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR.

Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.

The ADDR field

The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N:

N = Log2(Region size in bytes),

If the region size is configured to 4 Gbytes, in the MPU_RASR, there is no valid ADDR field.

In this case, the region occupies the complete memory map, and the base address is 0x00000000.

The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.

MPU region attribute and size register

The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.

MPU_RASR is accessible using word accesses:

• The most significant halfword holds the region attributes.

• The least significant halfword holds the region size and the region and subregion enable bits.

The bit assignments are:


The SIZE field defines the size of the MPU memory region specified by the RNR. as follows:

(Region size in bytes) = 2(SIZE+1)

The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The corresponding region size and value of N in the MPU_RBAR.

MPU 属性不匹配错误

When an access violates the MPU permissions, the processor generates a MemManage fault.

MemManage fault status register

The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are:

The MMFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

划分/更新 Region

To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASR registers. It is possible to program each register separately, or use a multiple word write to program all of these registers.

The MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM instruction.

简单的创建一个 Region 可以这么操作：

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute

重新设置一个已有的 region，更新它的属性或者重设区域大小，可以这么操作：

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable

The software must use memory barrier instructions:

• Before MPU setup if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings.

• After MPU setup if it includes memory transfers that must use the new MPU settings.

The software does not require any memory barrier instructions during MPU setup, because it accesses the MPU through the PPB, which is a Strongly-ordered memory region.

Subregions

Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR to disable a subregion.

The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, and the access is unprivileged or the background region is disabled, the MPU issues a fault.

Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, The user must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.

Example of SRD use

Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, set the SRD field for region two to 0b00000011 to disable the first two subregions, as the figure shows.