EGo1下板_简单秒表_2

最新推荐文章于 2023-12-04 23:15:32 发布

Bunny9__

最新推荐文章于 2023-12-04 23:15:32 发布

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分类专栏： Verilog实验

本文链接：https://blog.csdn.net/Bunny9__/article/details/115123895

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该博客介绍了一个基于FPGA的简单秒表设计，包括分频模块clk_use用于将100MHz时钟分频为1Hz，计数模块watch实现00.0到99.9的计数，数码管显示模块led通过分时复用显示计数值，以及顶层模块top将这些模块集成。约束文件con则定义了各I/O口的电气标准。

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1. 模块调用关系

r't'l

2. 分频模块clk_use

100MHz进行10_000_000分频

module clk_use(
    output  reg     clk_use,
    
    input   wire    clk_sys,
    input   wire    go,
    input   wire    clr
    );
    
    parameter   clk_count = 10_000_000;
    //parameter   clk_count = 4;
    reg     [23:0]  counter;
    //reg     [3:0]  counter;
    always @ (posedge clk_sys or negedge clr) begin
        if (clr == 1'b0) begin
            counter <=  24'b0;
        end else    begin
            if (go == 1'b1) begin
                if (counter >= clk_count)   counter <=  24'b0;
                else                        counter <=  counter + 1'b1;
            end else begin
                counter <=  counter;
            end
        end
    end
    
    always @ (counter)
        if ( counter == clk_count)  clk_use <=  1'b1;
        else                        clk_use <=  1'b0;
        
endmodule

3. 计数模块watch

00.0~99.9

module watch(
    output  reg     [3:0]   d2,
    output  reg     [3:0]   d1,
    output  reg     [3:0]   d0,
    
    input   wire            clk_use,
    input   wire            clr
    );
    
    
    always @ (posedge clk_use or negedge clr) begin
        if (clr == 1'b0) begin
            d2  <=  4'b0;
            d1  <=  4'b0;
            d0  <=  4'b0;
        end else begin
            if (d0 < 9) 
                d0  <=  d0 + 1'b1;
            else begin
                d0  <=  4'b0;
                if (d1 < 9)
                    d1 <= d1 + 1'b1;
                else begin
                    d1 <= 4'b0;
                    if (d2 < 9)
                        d2 <= d2 + 1'b1;
                    else begin
                        d2  <=  4'b0;
                    end
                end
            end
        end
    end
    
endmodule

4. 数码管显示模块led

这里用了多个组合逻辑和寄存器保存段选信号，但思想还是分时复用

module led(
    output  reg    [7:0]   seg,
    output  reg    [3:0]   an,
    
    input   wire            clk,
    input   wire            rst,
    input   wire    [3:0]   in2, in1, in0
    );
    
	   parameter   seg7_0 = ~8'hc0,    seg8_0 = ~8'h40;
	   parameter   seg7_1 = ~8'hf9,    seg8_1 = ~8'h79;
	   parameter   seg7_2 = ~8'ha4,    seg8_2 = ~8'h24;
	   parameter   seg7_3 = ~8'hb0,    seg8_3 = ~8'h30;
	   parameter   seg7_4 = ~8'h99,    seg8_4 = ~8'h19;
	   parameter   seg7_5 = ~8'h92,    seg8_5 = ~8'h12;
	   parameter   seg7_6 = ~8'h82,    seg8_6 = ~8'h02;
	   parameter   seg7_7 = ~8'hf8,    seg8_7 = ~8'h78;
	   parameter   seg7_8 = ~8'h80,    seg8_8 = ~8'h00;
	   parameter   seg7_9 = ~8'h90,    seg8_9 = ~8'h10;
	   parameter   _err = ~8'hcf;
	   
	   parameter   N = 18;
    
    reg     [7:0]   seg7_data2, seg8_data1, seg7_data0;   
    reg     [N-1 : 0]  regN; 
    reg     [3:0]       hex_in;
    
    always @ (posedge clk or posedge rst)   begin
        if (rst == 1'b0)    begin
            regN    <=  0;
        end else    begin
            regN    <=  regN + 1;
        end
    end
    always @ (*)    begin
        case (regN[N-1: N-2])
            2'b00:  begin
                an  <=  4'b0001;
                seg  <=  seg7_0;
            end
            2'b01:  begin
                an  <=  4'b0010;
                seg  <=  seg7_data0;
            end
            2'b10:  begin
                an  <=  4'b0100;
                seg  <=  seg8_data1;
            end
            2'b11:  begin
                an  <=  4'b1000;
                seg  <=  seg7_data2;
            end
            default:    begin
                an  <=  4'b1111;
                seg  <=  _err;
            end
        endcase
    end
	 
    always @ (*)    begin
        case (in2)
            4'h0:       seg7_data2 <= seg7_0;
            4'h1:       seg7_data2 <= seg7_1;
            4'h2:       seg7_data2 <= seg7_2;
            4'h3:       seg7_data2 <= seg7_3;
            4'h4:       seg7_data2 <= seg7_4;
            4'h5:       seg7_data2 <= seg7_5;
            4'h6:       seg7_data2 <= seg7_6;
            4'h7:       seg7_data2 <= seg7_7;
            4'h8:       seg7_data2 <= seg7_8;
            4'h9:       seg7_data2 <= seg7_9;
            default:    seg7_data2 <= _err;
        endcase
    end
    always @ (*)    begin
        case (in1)
            4'h0:       seg8_data1 <= seg8_0;
            4'h1:       seg8_data1 <= seg8_1;
            4'h2:       seg8_data1 <= seg8_2;
            4'h3:       seg8_data1 <= seg8_3;
            4'h4:       seg8_data1 <= seg8_4;
            4'h5:       seg8_data1 <= seg8_5;
            4'h6:       seg8_data1 <= seg8_6;
            4'h7:       seg8_data1 <= seg8_7;
            4'h8:       seg8_data1 <= seg8_8;
            4'h9:       seg8_data1 <= seg8_9;
            default:    seg8_data1 <= _err;
        endcase
    end
    
    always @ (*)    begin    
        case (in0)
            4'h0:       seg7_data0 = seg7_0;
            4'h1:       seg7_data0 = seg7_1;
            4'h2:       seg7_data0 = seg7_2;
            4'h3:       seg7_data0 = seg7_3;
            4'h4:       seg7_data0 = seg7_4;
            4'h5:       seg7_data0 = seg7_5;
            4'h6:       seg7_data0 = seg7_6;
            4'h7:       seg7_data0 = seg7_7;
            4'h8:       seg7_data0 = seg7_8;
            4'h9:       seg7_data0 = seg7_9;
            default:    seg7_data0 = _err;
        endcase
    end

endmodule

5. 顶层模块top

module top_stop_watch(
    output  wire     [3:0]  an,
    output  wire     [7:0]  seg,
    
    input   wire            clk_sys,
    input   wire            go,
    input   wire            clr
    );
    
    wire            clk_use;

    wire    [3:0]   data2;
    wire    [3:0]   data1;
    wire    [3:0]   data0;
    
    
    clk_use clk_use0 (
            .clk_use(clk_use), 
            .clk_sys(clk_sys), .go(go), .clr(clr)
            );
            
    watch   watch0  (
            .d2(data2), .d1(data1), .d0(data0),
            .clk_use(clk_use), .clr(clr)
            );
    led     led0    (
            .an(an), .seg(seg),
            .clk(clk_sys), .rst(clr), .in2(data2), .in1(data1), .in0(data0)
            );  
                 
endmodule

6. 约束文件con

set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {an[3]}]
set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {an[2]}]
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {an[1]}]
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {an[0]}]

set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg[0]}]
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg[1]}]
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg[2]}]
set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg[3]}]
set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg[4]}]
set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg[5]}]
set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg[6]}]
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg[7]}]

set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports clk_sys ]
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {clr}]
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {go}]