Hardware 部分缩写整理

本文纯属个人笔记瞎粘贴性质。

HPET: 

High Precision Event Timer

An HPET chip consists of a 64-bit up-counter (main counter) counting at a frequency of at least 10 MHz, and a set of (at least 3, up to 256) comparators. These comparators are 32- or 64-bit wide. The HPET is programmed via a memory mapped I/O window that is discoverable via ACPI. The HPET circuit in modern PCs is integrated into the southbridge chip.

TSC:

Time Stamp Counter

The instruction RDTSC returns the TSC in EDX:EAX.

the TSC cannot be relied on to provide accurate results — unless great care is taken to correct the possible flaws: rate of tick and whether all cores (processors) have identical values in their time-keeping registers.There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchronized.

这货可能不是单调递增，如果一个线程在多个核心上交替执行的话。它的tick频率也会随着CPU平率的改变而改变，而目前CPU为了节能都会根据loading是否重而改变自身频率。总之这货非专业勿用。。

APIC:

Advanced Programmable Interrupt Controller

Interrupt requests can be controlled using two ways:
1. At device end - An Interrupt Enable bit in a control register determines whether device is allowed to generate an interrupt request.
2. At processor end - A priority structure and an interrupt mask in the PS determine whether a given interrupt request is accepted.

Local APICs
LAPICs manage all external interrupts for some specific processor in an SMP system. In addition, it is able to accept and generate inter-processor interrupts (IPIs) between LAPICs. LAPICs may support up to 224 usable interrupt vectors from an I/O APIC. Vectors numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.
I/O APICs
I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs.

待续。。。