源代码:
module counter10(Q,CP,CR,Y);
input CP,CR;
output [0:3]Q;
output Y;
reg [0:3]Q;
assign Y=(Q==4'b1001);
always @(negedge CP or negedge CR)
if(~CR) Q<=4'b0000;
else if (Q==4'b1001) Q<=4'b0000;
else Q<=Q+1'b1;
endmodule
仿真:
用的是功能仿真;
源代码:
module counter10(Q,CP,CR,Y);
input CP,CR;
output [0:3]Q;
output Y;
reg [0:3]Q;
assign Y=(Q==4'b1001);
always @(negedge CP or negedge CR)
if(~CR) Q<=4'b0000;
else if (Q==4'b1001) Q<=4'b0000;
else Q<=Q+1'b1;
endmodule
仿真:
用的是功能仿真;