Verilog设计0到99两位十进制加法计数器

1.代码

module cnt10_2bit(clk,rst,en,out0,out1,data);
input clk,en,rst;
output [3:0] out0;
output [3:0] out1;
output [7:0] data;
reg [3:0] out0;//个位
reg [3:0] out1;//十位
wire [7:0] data;

always @(posedge clk or negedge rst)
   if(!rst)
      begin
         out0=0;
         out1=0;
      end
   else if(en)
      begin
         if(out0==9)
            begin
               out0<=0;
               out1=out1+1;
            end
         else
            out0<=out0+1;
         if(out1==10)
            out1<=0;
         else
            out1=out1;       
      end
assign data=(10*(out1))+out0;    
endmodule
				
					  

2.仿真波形