任意奇数次分频VHDL 源代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DEV3 IS
GENERIC (N:INTEGER :=3)
PORT(CLK,CLR:IN STD_LOGIC;
     CLKOUT:OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE RTL OF DEV3 IS
SIGNAL COUNTER1:INTEGER RANGE 0 TO N-1;
SIGNAL COUNTER2:INTEGER RANGE 0 TO N-1;
SIGNAL CLK_REG,CLK_REG1: STD_LOGIC;

BEGIN

PROCESS(CLR,CLK)
BEGIN
    
    IF CLR='1' THEN
       COUNTER1<=0;
       CLK_REG<='0';
    ELSIF CLK'EVENT AND CLK='1' THEN
       IF COUNTER1=N-1 THEN
          COUNTER1<=0;
          CLK_REG<=NOT CLK_REG;
       ELSIF COUNTER1=(N-1)/2 THEN
          COUNTER1<=COUNTER1+1;
          CLK_REG<=NOT CLK_REG;
       ELSE
            COUNTER1<=COUNTER1+1;
       END IF;
    END IF;
END PROCESS;

PROCESS(CLR,CLK)
BEGIN
    
    IF CLR='1' THEN
       COUNTER2<=0;
       CLK_REG1<='0';
    ELSIF CLK'EVENT AND CLK='0' THEN
       IF COUNTER2=N-1 THEN
          COUNTER2<=0;
          CLK_REG1<=NOT CLK_REG;
       ELSIF COUNTER2=(N-1)/2 THEN
          COUNTER2<=COUNTER2+1;
          CLK_REG1<=NOT CLK_REG1;
       ELSE
            COUNTER2<=COUNTER2+1;
       END IF;
    END IF;
END PROCESS;

CLKOUT<=CLK_REG OR CLK_REG1;

END RTL;