汉明纠错吗编码器(VHDL)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY hamenc IS
   PORT(datain : IN BIT_VECTOR(0 TO 3);    --d0 d1 d2 d3
        hamout : OUT BIT_VECTOR(0 TO 7));  --d0 d1 d2 d3 p0 p1 p2 p4
END hamenc;

ARCHITECTURE ver2 OF hamenc IS

   SIGNAL p0, p1, p2, p4 : BIT;    --check bits

BEGIN

      
   --generate check bits
   p0 <= (datain(0) XOR datain(1)) XOR datain(2);
   p1 <= (datain(0) XOR datain(1)) XOR datain(3);
   p2 <= (datain(0) XOR datain(2)) XOR datain(3);
   p4 <= (datain(1) XOR datain(2)) XOR datain(3);

   --connect up outputs
   hamout(4 TO 7) <= (p0, p1, p2, p4);
   hamout(0 TO 3) <= datain(0 TO 3);

END ver2;