verilog实现计数器

/*********在闸门时间内对clk脉冲个数进行计数*************/
module cnt(clk,gate,cntout);

input clk;
input gate;
output [19:0] cntout ;

reg [19:0] cnt,cntout;
reg gatebuf;

always @(posedge clk)
begin
    gatebuf<=gate;
end

always @(posedge clk)
begin
    if((gate==1'b1)&&(gatebuf==1'b0))//门信号的上升沿
    begin
        cnt<=20'd1;//开始计数