verilog中几种实现计数器的方法

1、if语句实现计数器

module counter (

input clk,

output reg [3:0] count

);

always @(posedge clk)

begin

if (count == 4’hF)

begin

count <= 4’h0;

end

else

begin

count <= count + 4’b1;

end

end

endmodule

2、 for 循环语句实现计数器

integer      i ;

reg [3:0]    counter2 ;

initial begin

    counter2 = 'b0 ;

    for (i=0; i<=10; i=i+1) begin

        #10 ;

        counter2 = counter2 + 1'b1 ;

    end

End

3、while语句实现计数器

module test ;

      reg [3:0]    counter ;

    initial begin

        counter = 'b0 ;

        while (counter<=10) begin

            #10 ;

            counter = counter + 1'b1 ;

        end

    end

  

   //stop the simulation

    always begin

        #10 ;  if ($time >= 1000) $finish ;

    end

  

Endmodule

4、 repeat 循环语句实现计数器

reg [3:0]    counter3 ;

initial begin

    counter3 = 'b0 ;

    repeat (11) begin  //重复11次

        #10 ;

        counter3 = counter3 + 1'b1 ;

    end

End

//、for语句打印出count的值。

module for_example;

  reg [7:0] count;

  initial

    begin

      count = 0;

      for(count = 0; count < 8; count = count + 1)

        $display("count = %d", count);

    end

Endmodule

//while语句打印出count的值。

module while_example;

  reg [7:0] count;

  initial

    begin

      count = 0;

      while(count < 8)

        begin

          $display("count = %d", count);

          count = count + 1;

        end

    end

endmodule