四位行波进位加法器相当于四个全加器的级联
先设计全加器fa.v
module fa(a, b, ci, sum, cout);
input a, b, ci;
output sum, cout;
assign {cout, sum} = a + b + ci;
endmodule
四位加法器add4.v
module add4(a, b, ci, s, cout);
input [3:0] a, b;
input ci;
output cout;
output [3:0] s;
wire [3:1] co;
fa u1(a[0], b[0], ci, s[0], co[1]);
fa u2(a[1], b[1], co[1], s[1], co[2]);
fa u3(a[2], b[2], co[2], s[2], co[3]);
fa u4(a[3], b[3], co[3], s[3], cout);
endmodule
add4tb.v
`timescale 1ns/1ns
module add4tb;
reg [3:0] a_test, b_test;
wire [3:0] sum_test;
reg cin_test;
wire cout_test;
reg [9:0] test;
integer error_count;
add4 u1( .a(a_test), .b(b_test), .ci(cin_test), .s(sum_test), .cout(cout_test) );
initial
begin
error_count = 0;
`ifdef vcdplusdump
$display("\n*** VCD+ file dump is turned on ***\n");
$vcdpluson;
#1000;
$vcdplusoff;
`endif
`ifdef vcddump
$display("\n*** VCD file dump is turned on ***\n");
$dumpvars;
// #1000;
// $dumpoff;
`endif
`ifdef fsdbdump
$display("\n*** fsdb file dump is turned on ***\n");
$fsdbDumpfile("add4.fsdb");
$fsdbDumpvars(0);
// #1000
// $fsdbDumpoff;
`endif
end
initial
begin
for (test = 0; test <= 9'h1ff; test = test +1) begin
cin_test = test[8];
a_test = test[7:4];
b_test = test[3:0];
#50
if ({cout_test, sum_test} !== (a_test + b_test + cin_test)) begin
error_count = error_count + 1;
if (error_count <= 10) begin
$display("***ERROR at time = %0d ***", $time);
$display("a = %h, b = %h, sum = %h; cin = %h, cout = %h",
a_test, b_test, sum_test, cin_test, cout_test);
end
if (error_count == 10) begin
$display("\n\nError count reached 10, subsequent error messages are suppressed");
`ifdef vcdplusdump
$vcdplusoff;
$vcdplusdeltacycleoff;
$vcdplusglitchoff;
`endif
`ifdef vcddump
$dumpoff;
`endif
`ifdef fsdbdump
$fsdbDumpoff;
`endif
end
end
#50;
end
if (error_count == 0)
$display("*** Testbench Successfully Completed! ***");
else begin
$display("\n*********************************************");
$display("*** Testbench completed with %0d errors ***",error_count);
$display("*********************************************\n\n");
end
$finish;
end
endmodule
Verdi仿真结果