FPGA project : full_adder

 

module full_adder(
    input         wire        data_1 ,
    input         wire        data_2 ,
    input         wire        cin_1  ,

    output        wire        count  ,
    output        wire        sum             
);

    wire                      count_r_1 ;
    wire                      sum_r_1   ;
half_adder half_adder_insert_1 (
    .data_1                 ( data_1    ) ,
    .data_2                 ( data_2    ) ,
    .count                  ( count_r_1 ) ,
    .sum                    ( sum_r_1   )
);

    wire                      count_r_2 ;
half_adder half_adder_insert_2 (
    .data_1                 ( sum_r_1   ) ,
    .data_2                 ( cin_1     ) ,
    .count                  ( count_r_2 ) ,
    .sum                    ( sum       )
);

    assign count = count_r_1 || count_r_2 ;

endmodule

module half_adder(
    input        wire       data_1      ,
    input        wire       data_2      ,
    output       wire       count       ,
    output       wire       sum      
);

    assign { count, sum } = data_1 + data_2 ;
    
endmodule

`timescale 1ns/1ps
module test();
    reg           data_1_tb  ;
    reg           data_2_tb  ;
    reg           cin_1_tb   ;

    wire          count_tb   ;
    wire          sum_tb     ;

full_adder full_adder_insert(
    .data_1     ( data_1_tb) ,
    .data_2     ( data_2_tb) ,
    .cin_1      ( cin_1_tb ) ,

    .count      ( count_tb ) ,
    .sum        ( sum_tb   )             
);

    parameter CYCLE = 20 ;

    initial begin
        data_1_tb <= 1'b0 ;
        data_2_tb <= 1'b0 ;
        cin_1_tb  <= 1'b0 ;
        #( CYCLE * 1000 ) ;
        $stop ;
    end

    always #( CYCLE * 5 ) data_1_tb <= ($random) % 2 ;
    always #( CYCLE * 5 ) data_2_tb <= ($random) % 2 ;
    always #( CYCLE * 5 ) cin_1_tb  <= ($random) % 2 ;

    initial begin
        $timeformat(-9, 0, "ns", 6) ;
        $monitor("@time%t: data_1_tb=%b, data_2_tb=%b, cin_1_tb=%b, count_tb=%b, sum=%b ",$time, data_1_tb, data_2_tb, cin_1_tb, count_tb, sum_tb) ;
    end

endmodule