module cap_key (
input wire sys_clk ,
input wire sys_rst_n ,
input wire cap_key ,
output reg cap_key_ctrl
);
// signal define
reg cap_key_r0 ;
reg cap_key_r1 ;
wire nege ;
// cap_key_r0 cap_key_r1
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cap_key_r0 <= 1'b0 ;
end else begin
cap_key_r0 <= cap_key ;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cap_key_r1 <= 1'b0 ;
end else begin
cap_key_r1 <= cap_key_r0 ;
end
end
// nege
assign nege = ~cap_key_r0 && cap_key_r1 ;
// cap_key_ctrl
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cap_key_ctrl <= 1'b1 ;
end else begin
if(nege) begin
cap_key_ctrl <= ~cap_key_ctrl ;
end else begin
cap_key_ctrl <= cap_key_ctrl ;
end
end
end
endmodule
`timescale 1ns/1ns
module test();
reg sys_clk ;
reg sys_rst_n ;
reg cap_key ;
wire cap_key_ctrl ;
parameter CYCLE = 20 ;
cap_key cap_key_insert (
.sys_clk ( sys_clk ) ,
.sys_rst_n ( sys_rst_n ) ,
.cap_key ( cap_key ) ,
.cap_key_ctrl ( cap_key_ctrl )
);
initial begin
sys_clk = 1'b1 ;
sys_rst_n = 1'b0 ;
#(CYCLE * 5) ;
sys_rst_n = 1'b1 ;
#(30) ;
sys_rst_n = 1'b0 ;
#(50) ;
sys_rst_n = 1'b1 ;
#(CYCLE * 1000) ;
end
initial begin
cap_key <= 1 ;
#(110) ;
cap_key <= 0 ;
#(210) ;
cap_key <= 1 ;
#(310) ;
cap_key <= 0 ;
#(410) ;
cap_key <= 1 ;
cap_key <= 0 ;
#(210) ;
cap_key <= 1 ;
#(310) ;
cap_key <= 0 ;
#(410) ;
cap_key <= 1 ;
#(510) ;
$stop ;
end
always #(CYCLE / 2) sys_clk = ~sys_clk;
endmodule