module half_adder(
input wire data_1 ,
input wire data_2 ,
output reg count ,
output reg sum
);
always @(*) begin
case ({data_1, data_2})
2'b00 : begin
count = 0 ;
end
2'b01 : begin
count = 0 ;
end
2'b10 : begin
count = 0 ;
end
2'b11 : begin
count = 1 ;
end
default: count = 1'bz ;
endcase
end
always @(*) begin
case ({data_1, data_2})
2'b00 : begin
sum = 0 ;
end
2'b01 : begin
sum = 1 ;
end
2'b10 : begin
sum = 1 ;
end
2'b11 : begin
sum = 0 ;
end
default: sum = 1'bz ;
endcase
end
endmodule
`timescale 1ns/1ps
module test();
reg data_1_tb ;
reg data_2_tb ;
wire count_tb ;
wire sum_tb ;
half_adder half_adder_insert(
.data_1 ( data_1_tb ) ,
.data_2 ( data_2_tb ) ,
.count ( count_tb ) ,
.sum ( sum_tb )
);
parameter CYCLE = 20 ;
initial begin
data_1_tb <= 1'b1 ;
data_2_tb <= 1'b1 ;
#( CYCLE * 1000 ) ;
$stop ;
end
always #( CYCLE ) data_1_tb <= ($random) % 2 ;
always #( CYCLE ) data_2_tb <= ($random) % 2 ;
initial begin
$timeformat(-9,0,"ns",6) ;
$monitor("@time %t:data_1_tb=%b,data_2_tb=%b,count_tb=%b,sum_tb=%b",$time,data_1_tb,data_2_tb,count_tb,sum_tb) ; // 监测函数
end
endmodule
module half_adder(
input wire data_1 ,
input wire data_2 ,
output wire count ,
output wire sum
);
assign { count, sum } = data_1 + data_2 ;
endmodule