systemverilog中门类型-2-双向通过开关bidirectional pass switches

双向通过开关主要有tran/rtran/tranif0/tranif1/rtranif0/rtranif1

当tranif0,tranif1, rtranif0, or rtranif1设备关闭时,它们应该阻塞信号。当打开时,它们应该通过信号。而tran and rtran 设备不能被关闭,它们一直通过信号。

实例tranif1声明语法:
tranif1 t1 (inout1,inout2,control);

1.延迟规格
The delay specifications for** tranif1, tranif0, rtranif1, and rtranif0 **devices shall be zero, one, or two delays.
If the specification contains two delays, the first delay shall determine the turn-on delay, the second delay shall determine the turn-off delay, and the smaller of the two delays shall apply to output transitions to x and z.
If only one delay is specified, it shall specify both the turn-on and the turn-off delays.
If there is no delay specification, there shall be no turn-on or turn-off delay for the bidirectional pass switch.

双向通过开关tran和rtran没有延迟使用。

The tranif1, tranif0, rtranif1, and rtranif0 devices shall have three items in their terminal lists.
前两个选项是信号输入与输出信号,第三个是输出信号控制开关。
这两个开关tran和rtran包含两个双向信号。这六个开关应该是标量网线或向量位选。

这些开关tran, tranif0, and tranif1 只有一种情况会改变通过信号的强度, as discussed in 28.15.1. 这些开关rtran, rtranif0, and rtranif1 会降低通过它们信号的强度,as discussed in 28.14.

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回答: 在Verilog中,tran是一种设备,它在其终端列表中有三个项。前两个选项是信号输入和输出信号,第三个是输出信号控制开关tran开关包含两个双向信号,可以是标量网线或向量位选。\[2\] tran设备用于实现双向传输,可以在输入和输出之间传输数据。它可以在不同的时钟边沿触发,并根据控制信号的状态来决定数据的传输方向。tran设备通常用于实现总线接口。 #### 引用[.reference_title] - *1* [Verilog-程序设计语句-三种建模方式](https://blog.csdn.net/weixin_43239805/article/details/123824621)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] - *2* [systemverilog中门类型-2-双向通过开关bidirectional pass switches](https://blog.csdn.net/Michael177/article/details/121090896)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] - *3* [Verilog HDL复习总结](https://blog.csdn.net/jingyu_1/article/details/125485833)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] [ .reference_list ]
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