瑞芯微rockchip PX30 显示屏调试记录

系列文章目录

瑞芯微rockchip PX30 串口调试记录
瑞芯微rockchip PX30 显示屏调试
瑞芯微rockchip PX30触摸屏调试记录
瑞芯微rockchip PX30 QT环境搭建
瑞芯微rockchip PX30 GPIO的使用

---

1、开发环境

  系统：ubuntu 16.04
  芯片：瑞芯微PX30
  SDK：rk官方SDK V1.5.0
  内核版本：Linux 4.4.194
  PX30接口：LCDC M1
  屏幕型号：AVD-TT50WV-CN
  屏幕接口：RGB888

  注意：本文档的修改适用于PX30 Linux最新的SDK，可能不适用于旧版本的SDK，新版本的SDK对于LCDC M1进行了修改，逻辑上LCDC M1不会再由lvds配置驱动。
                            ————2021年7月10日

2、显示屏参数信息

2.1、显示参数

每帧显示时长：
（800+8+8+4）*（480+8+8+4） = 410000
60帧显示需要的时钟：
410000 * 60 = 24,600,000

2.2、显示屏引脚信息

3、硬件接口信息

LCD接口	PX30接口	说明
RGB和信号线	LCDC m1	部分为lvds驱动，部分为io口
DISP	GPIO3_B7	0为standby；1为显示（通常拉高）
BL	PWM1	PWM1
BL_EN	GPIO0_B5	0为息屏；1为亮屏

4、设备树文件修改

4.1、新建设备树文件（lcd-rgb800x480-xxxx.dtsi）

/*
 * Copyright (C) 2021 zhangshiqun
 * lcd model: AVD-TT50WV
 * resolution: 800x480
 * 5 inch rgb interface 800x480
 */
/ {
	panel {
		compatible = "simple-panel";
		backlight = <&backlight>;
		enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; 
		bus-format = <MEDIA_BUS_FMT_RBG888_1X24>;
		enable-delay-ms = <20>;
		prepare-delay-ms = <20>;
		unprepare-delay-ms = <20>;
		disable-delay-ms = <20>;
		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <24600000>;		//(800+8+8+4)*(480+8+8+4) * 60帧
				hactive = <800>;
				vactive = <480>;
				hback-porch = <8>;
				hfront-porch = <8>;
				vback-porch = <8>;
				vfront-porch = <8>;
				hsync-len = <4>;
				vsync-len = <4>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <0>;
				pixelclk-active = <0>;
				swap-rb = <0>;
				swap-rg = <0>;
				swap-gb = <0>;
			};
		};
		ports {
			panel_in_rgb: endpoint {
				remote-endpoint = <&rgb_out_panel>;
			};
		};
	};
};


&display_subsystem {
	status = "okay";
};


&rgb {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;

			rgb_out_panel: endpoint {
				remote-endpoint = <&panel_in_rgb>;
			};
		};
	};
};

&rgb_in_vopb {
	status = "okay";
};

&rgb_in_vopl {
	status = "disabled";
};

&route_rgb {
	status = "okay";
};

4.2、修改背光配置

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 10000 0>;
		enable-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
		brightness-levels = <
			  0   1   2   3   4   5   6   7
			  8   9  10  11  12  13  14  15
			 16  17  18  19  20  21  22  23
			 24  25  26  27  28  29  30  31
			 32  33  34  35  36  37  38  39
			 40  41  42  43  44  45  46  47
			 48  49  50  51  52  53  54  55
			 56  57  58  59  60  61  62  63
			 64  65  66  67  68  69  70  71
			 72  73  74  75  76  77  78  79
			 80  81  82  83  84  85  86  87
			 88  89  90  91  92  93  94  95
			 96  97  98  99 100 101 102 103
			104 105 106 107 108 109 110 111
			112 113 114 115 116 117 118 119
			120 121 122 123 124 125 126 127
			128 129 130 131 132 133 134 135
			136 137 138 139 140 141 142 143
			144 145 146 147 148 149 150 151
			152 153 154 155 156 157 158 159
			160 161 162 163 164 165 166 167
			168 169 170 171 172 173 174 175
			176 177 178 179 180 181 182 183
			184 185 186 187 188 189 190 191
			192 193 194 195 196 197 198 199
			200 201 202 203 204 205 206 207
			208 209 210 211 212 213 214 215
			216 217 218 219 220 221 222 223
			224 225 226 227 228 229 230 231
			232 233 234 235 236 237 238 239
			240 241 242 243 244 245 246 247
			248 249 250 251 252 253 254 255>;
		default-brightness-level = <10>;
	};

4.3、修改px30-evb-ddr3-v10-linux.dts

&lvds {
	ports {
		port@0 {
			/delete-node/ endpoint@1;
		};
	};
};

&rgb {
	phys = <&video_phy>;
	phy-names = "phy";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&lcdc_m1_rgb_pins>;
	pinctrl-1 = <&lcdc_m1_sleep_pins>;

	ports {
		port@0 {
			/delete-node/ endpoint@1;
		};
	};
};

4.4、修改px30.dtsi

	vopl: vop@ff470000 {
		compatible = "rockchip,px30-vop-lit";
		reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>;
		rockchip,grf = <&grf>;
		reg-names = "regs", "gamma_lut";
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
			 <&cru HCLK_VOPL>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power PX30_PD_VO>;
		iommus = <&vopl_mmu>;
		status = "disabled";

		vopl_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vopl_out_lvds: endpoint@0 {
			//	reg = <0>;
			//	remote-endpoint = <&lvds_in_vopl>;
			};

			vopl_out_dsi: endpoint@1 {
			//	reg = <1>;
			//	remote-endpoint = <&dsi_in_vopl>;
			};

			vopl_out_rgb: endpoint@2 {
			//	reg = <2>;
			//	remote-endpoint = <&rgb_in_vopl>;
			};
		};
	};

5、开机Log输出

Starting kernel …
…
[ 1.184418] [drm] Initialized drm 1.1.0 20060810
[ 1.191222] [drm] Rockchip DRM driver version: v1.0.1
[ 1.191399] [drm] component_match_realloc done
[ 1.191408] [drm] return with component_master_add_child ret = 0
[ 1.191669] rockchip-drm display-subsystem: devfreq is not set
[ 1.192746] rockchip-drm display-subsystem: bound ff460000.vop (ops 0xffffff8008a3af28)
[ 1.192954] rockchip-rgb ff140000.syscon:rgb: [drm:rockchip_rgb_bind] ERROR failed to find panel or bridge: -517
[ 1.192975] rockchip-drm display-subsystem: failed to bind ff140000.syscon:rgb (ops 0xffffff8008a327b8): -517
[ 1.193487] rockchip-drm display-subsystem: master bind failed: -517
[ 1.193494] [drm] ret = -517
…
…
[ 3.036028] [drm] Rockchip DRM driver version: v1.0.1
[ 3.036205] [drm] component_match_realloc done
[ 3.036211] [drm] return with component_master_add_child ret = 0
[ 3.036396] rockchip-drm display-subsystem: devfreq is not set
[ 3.037197] rockchip-drm display-subsystem: bound ff460000.vop (ops 0xffffff8008a3af28)
[ 3.037445] rockchip-drm display-subsystem: bound ff140000.syscon:rgb (ops 0xffffff8008a327b8)
[ 3.037453] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.037456] [drm] No driver support for vblank timestamp query.
[ 3.054349] mmc_host mmc2: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 3.184912] rockchip-drm display-subsystem: fb0: frame buffer device
[ 3.196716] [drm] ret = 1
…

6、Summary查看

[root@px30_64:/]# cat /sys/kernel/debug/dri/0/summary
VOP [ff460000.vop]: ACTIVE
    Connector: DPI
        overlay_mode[0] bus_format[100e] output_mode[0] color_space[0]
    Display mode: 800x480p60
        clk[24600] real_clk[24600] type[8] flag[a]
        H: 800 808 812 820
        V: 480 488 492 500
    win0-0: DISABLED
    win1-0: ACTIVE
        format: AR24 little-endian (0x34325241) SDR[0] color_space[0]
        csc: y2r[0] r2r[0] r2y[0] csc mode[0]
        zpos: 0
        src: pos[0x0] rect[800x480]
        dst: pos[0x0] rect[800x480]
        buf[0]: addr: 0x0000000000237000 pitch: 3200 offset: 0
    win2-0: DISABLED
    win2-1: DISABLED
    win2-2: DISABLED
    win2-3: DISABLED
    post: sdr2hdr[0] hdr2sdr[0]
    pre : sdr2hdr[0]
post CSC: r2y[0] y2r[0] CSC mode[1]
[root@px30_64:/]#

  旧版本的SDK在Connector的属性为LVDS，新版本区分后RGB的Connector熟悉变为DPI。

7、参考文件

  SDK/docs/Common/DISPLAY/Rockchip_DRM_Display_Driver_Development_Guide_V1.0.pdf
  SDK/docs/Common/DISPLAY/Rockchip_DRM_Panel_Porting_Guide_V1.6_20190228.pdf
  SDK/docs/Common/DISPLAY/rockchip_drm_integration_helper-zh.pdf
  SDK/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt
  SDK/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
  SDK/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-rgb.txt
  SDK/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-backlight.txt
  SDK/kernel/Documentation/devicetree/bindings/display/panel/simple-panel.txt

---

分割线，（2021年8月2日）

---

8、屏幕方向调整

  由于所用的文件系统为SDK编译时使用的buildroot，其中界面的显示服务默认使用Weston 8.0drm后端。Weston的屏幕显示方向可以在weston.ini的output段配置，如：

# /etc/xdg/weston/weston.ini
[output]
name=LVDS-1
transform=90
# normal|90|180|270|flipped|flipped-90|flipped-180|flipped-270 

  如果需要动态配置屏幕方向，可以通过动态配置文件，如：

echo "output:all:rotate90" > /tmp/.weston_drm.conf # 所有屏幕旋转90度
echo "output:eDP-1::rotate180" > /tmp/.weston_drm.conf # eDP-1旋转180度