VHDL syntax error at near text问题如何解决

代码：
begin

singal sub_wire0:std_logic_vector (3 downto 0);

component lpm_constant
generic(
lpm_cvalue : natural;
lpm_width : natural
);
port (
result : out std_logic_vector (3 downto 0)
) ;
end component;

错误提示：
Error (10500): VHDL syntax error at fangbo.vhd(91) near text “sub_wire0”; expecting “(”, or “’”, or “.”