Avalon总线转寄存器操作

//
module Avalon2reg
#(
	parameter	ADDR_WIDTH	= 16
)
(
    input               		clk                     	,
    input               		reset_n                 	,
    /
	//add regiester begin
	output	[31:0]				reg1						,
	//add regiester end
	
    input						avalon_rd                	,
    input               		avalon_wr               	,
    input   [ADDR_WIDTH - 1:0]	avalon_addr                	,
    input   [31:0]      		avalon_wr_data             	,
    output  [31:0]      		avalon_rd_data                      
);
/
//read
reg	[31:0]	avalon_rd_data_r;
assign avalon_rd_data = avalon_rd_data_r;
//---------------------------------------------
always @(posedge clk or negedge reset_n)
begin
  if(!reset_n)
    avalon_rd_data_r <= 32'd0;
  else if(avalon_rd == 1'b1)
  begin
    case(avalon_addr[ADDR_WIDTH - 1:0])
		//
		'h0000	:	avalon_rd_data_r <= reg1			;

	
      default :avalon_rd_data_r <= 32'hFFFFFFFF				;//访问未定义寄存器
    endcase
  end
  else
	avalon_rd_data_r <= avalon_rd_data_r;
end    
/


//write
//
reg_gen #(32,0) u_h0000(clk,reset_n,'h0000,avalon_wr,avalon_addr,avalon_wr_data,reg1);			

//


endmodule





//
module reg_gen 
#(
	parameter 	WIDTH 		= 32	,
	parameter 	INIT_VALUE 	= 0			
)
(
	input 					clk				,
	input 					rst_n			,
	
	input	[15:0]			reg_addr		,
	
	input 					avalon_wr			,
	input	[15:0]			avalon_addr		,
	input  	[31:0]			avalon_wr_data		,
	
	output  [WIDTH-1:0]		reg_dout			

);

reg [WIDTH-1:0] reg_dout_d = INIT_VALUE;

assign reg_dout = reg_dout_d;

always@(posedge clk or negedge rst_n)
begin
	if(rst_n == 1'b0)
		reg_dout_d <= INIT_VALUE;
	else if((avalon_wr == 1'b1) && (avalon_addr == reg_addr))
		reg_dout_d <= avalon_wr_data;
	else 
		reg_dout_d <= reg_dout_d;
end





endmodule