2018/08/29更新:Verilog HDL语言设计规范中讲到:一个reg变量只能在一个always语句中赋值,下面的问题就违反了这个原则。
更多规范见我的另一篇博文:Verilog HDL 使用规范(一)
用状态机描述转移图的方式,去设计一个模为5的计数器。出现了一系列的问题,一度让我崩溃。最终找到了问题的来源,且看问题以及排错过程。
问题如题目,我的代码为:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 22:12:23 08/03/2018
// Design Name:
// Module Name: counter5
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module counter5(clk,rst, cnt, co);
input clk;
input rst;
output[2:0] cnt;
output co;
reg co;
reg[2:0] pre_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
pre_state <= s0;
co <= 1'b0;
end
else
begin
pre_state <= next_state;
end
end
always@(pre_state)
begin
case(pre_state)
s0:
begin
next_state = s1;
co = 1'b0;
end
s1:
begin
next_state = s2;
co = 1'b0;
end
s2:
begin
next_state = s3;
co = 1'b0;
end
s3:
begin
next_state = s4;
co = 1'b0;
end
s4:
begin
next_state = s0;
co = 1'b1;
end
default:
begin
next_state = s0;
co = 1'b0;
end
endcase
end
assign cnt = pre_state;
endmodule
此代码在Modelsim中进行功能仿真完全没问题,仿真图如下:
然后,我就在ISE中进行综合,然后总会综合失败,且报错如下:
Line 32: Signal co in unit counter5 is connected to following multiple drivers:
Driver 0: output signal co of instance pre_state[2]_GND_1_o_Mux_2 (pre_state[2]_GND_1_o_Mux_2).
Driver 1: output signal co of instance Latch (co).
Module counter5 remains a blackbox, due to errors in its contents
WARNING:HDLCompiler:1499 - "G:\ISE_file\cnt5\cnt5.v" Line 21: Empty module <counter5> remains a black box.
-->
Total memory usage is 204416 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
红色部分是我最终找到问题的关键,它的意思是我的co出问题了。那我们看我们代码中的co。
在如下部分always中出现了一次:
always@(posedge clk or posedge rst)
begin
if(rst)
begin
pre_state <= s0;
co <= 1'b0;
end
else
begin
pre_state <= next_state;
endend
在下面always中又出现各种赋值:
always@(pre_state)
begin
case(pre_state)
s0:
begin
next_state = s1;
co = 1'b0;
end
s1:
begin
next_state = s2;
co = 1'b0;
end
s2:
begin
next_state = s3;
co = 1'b0;
end
s3:
begin
next_state = s4;
co = 1'b0;
end
s4:
begin
next_state = s0;
co = 1'b1;
end
default:
begin
next_state = s0;
co = 1'b0;
end
endcase
end
这个co的赋值在下面一个always中是必须的,由于这是我在不同状态下的输出,因此这个不能动,那么我就注释掉上面的一个always中的co,那个赋值不要也行,赋值在下面一个always块中也能完成,因此问题可能出现在这个地方,注释掉了之后,奇迹出现了综合通过。
贴出最终代码:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 22:12:23 08/03/2018
// Design Name:
// Module Name: counter5
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module counter5(clk,rst, cnt, co);
input clk;
input rst;
output[2:0] cnt;
output co;
reg co;
reg[2:0] pre_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
pre_state <= s0;
end
else
begin
pre_state <= next_state;
end
end
always@(pre_state)
begin
case(pre_state)
s0:
begin
next_state = s1;
co = 1'b0;
end
s1:
begin
next_state = s2;
co = 1'b0;
end
s2:
begin
next_state = s3;
co = 1'b0;
end
s3:
begin
next_state = s4;
co = 1'b0;
end
s4:
begin
next_state = s0;
co = 1'b1;
end
default:
begin
next_state = s0;
co = 1'b0;
end
endcase
end
assign cnt = pre_state;
endmodule
Modelsim中仿真同样没问题,ISE中综合也能通过了。综合出来的RTL原理图为:
虽然分析如此,但是这个分析的过程远比这个复杂的多,由于没遇到过这种情况,让我几乎崩溃。还好最终解决了这个问题。
后来,貌似也搜到了网上其他同学类似的问题,地址如下:
verilog程序,ISE 10.1环境下,检查语法和仿真均可,综合出错“ this signal is connected to multiple drivers.”
这位同学的意思是:
此类错误系将某同一个reg变量在多个个always块中进行了赋值操作,此类程序是不可综合的,因此须修改程序。
切记,对于同一个reg型变量只能在一个always块中对其值进行修改,当然在其它块中可以引用其值!
总结的真不错,很感谢哎!