FPGA时序案例分析【Vivado版】

时序问题一直是一个难以理解的难点，这里通过一个简单的实际案例来学习下时序分析，以及解决的方案。

本博文使用Vivado来进行测试分析。

下面给出测试代码：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/03/19 09:58:03
// Design Name: 
// Module Name: time_analyze
// 
//


module time_analyze(
    input [4:0] data_in,
    input clk,
    input reset,
    output reg [4:0] data_out
    );
    
    reg [4:0] data_tmp_in;
    wire [4:0] data_tmp_out;
    wire [4:0] data_tmp2,data_tmp3,data_tmp4,data_tmp5,data_cal_out;
    
    always@ (posedge clk) begin
        if(reset) data_tmp_in <= 0;
        else data_tmp_in <= data_in;
    end
    
    //连续乘法，增加逻辑门数量
    assign data_tmp2 = data_tmp_in * 3;
    assign data_tmp3 = data_tmp2 * data_tmp_in;
    assign data_tmp4 = data_tmp3 * data_tmp2;
    assign data_tmp5 = data_tmp4 * data_tmp3;
    assign data_cal_out = data_tmp5;
    
    always@ (posedge clk) begin
        if(reset) data_out <= 0;
        else data_out <= data_cal_out;
    end
    
    
endmodule

代码说明：

从测试代码可以看出，本测试故意使用多级乘法来增加逻辑延迟，故意让时序尽可能不满足。

    assign data_tmp2 = data_tmp_in * 3;
    assign data_tmp3 = data_tmp2 * data_tmp_in;
    assign data_tmp4 = data_tmp3 * data_tmp2;
    assign data_tmp5 = data_t