我们从上电后的第一个函数说起：SystemInit函数
跳转到定义：
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef STM32F10X_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
这是这个函数的源码，执行的第一句代码是RCC->CR |= (uint32_t)0x00000001;，注释中写的很明白，将HSION（High Speed Internal Clock ON）位进行置位，结合寄存器我们可以进一步理解：
下标rw表示read write，即可读可写
所以这句代码的作用就是使能了内部高速时钟。
接着下面都是一些由 #ifndef 、 #ifdef 以及 #endif 组成的预处理指令。这些预处理指令在stm32f10x.h文件中被定义：
如果我们不作修改，那么这些宏定义都不会被放开。有关于这些宏定义的解释，大家可以阅读这篇文章：STM32F10X_LD、STM32F10X_MD、STM32F10X_HD、STM32F10X_CL、STM32f10X_XL、STM32f10X_VL区别和用法_stm32f103的cl hd ld区别-CSDN博客
（按照上面的文章f103系列应该属于xl超高密度产品，后面我会试一下放开这个宏定义会发生什么）
既然这些宏定义都没有被放开，那么就会进入第一条预处理指令 #ifndef STM32F10X_CL ，进入里面后执行 RCC->CFGR &= (uint32_t)0xF8FF0000; （1111 1000 1111 1111 0000 0000 0000 0000）这句代码，结合注释我们可以知道这句代码是为了reset这个寄存器中的一些位，所有带零的位都会被reset（因为进行了&操作）。结合寄存器描述我们来看一下：
![![[Pasted image 20240717183713.png]]](https://i-blog.csdnimg.cn/direct/c8b8bcaa3778437cad952746e43e505d.png)
![![[Pasted image 20240717183753.png]]](https://i-blog.csdnimg.cn/direct/05690635f6ff404caa8aeacb55d5361a.png)
![![[Pasted image 20240717183809.png]]](https://i-blog.csdnimg.cn/direct/2ed59fd4904642ac8886aed3abeb3207.png)
![![[Pasted image 20240717184041.png]]](https://i-blog.csdnimg.cn/direct/6a8b8748de0c4b099fd49b75e30e16e1.png)
![![[Pasted image 20240717184101.png]]](https://i-blog.csdnimg.cn/direct/0c68dccc3a8746ad865bbc4961a82be7.png)
![![[Pasted image 20240717184134.png]]](https://i-blog.csdnimg.cn/direct/05b248f99b764f1b968553743fb03608.png)
![![[Pasted image 20240717184652.png]]](https://i-blog.csdnimg.cn/direct/057e55654f0f47a388d81aff603af6c1.png)
之前没有接触过这个功能，上网搜了一下资料，MCO这三位可以将32时钟信号从引脚进行输出。
STM32的复用功能——时钟输出(MCO)_时钟输出功能的作用-CSDN博客
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
![![[Pasted image 20240717190042.png]]](https://i-blog.csdnimg.cn/direct/fbad928531ec4c7e8bb8517b7f1599f5.png)
![![[Pasted image 20240717190017.png]]](https://i-blog.csdnimg.cn/direct/e60dcb13a2814ee697496122234c3ef8.png)
![![[Pasted image 20240717190354.png]]](https://i-blog.csdnimg.cn/direct/8f6bdd6ab70746a79a508bc1b6417214.png)
![![[Pasted image 20240717190421.png]]](https://i-blog.csdnimg.cn/direct/ae7dd52fb82b4b9daced404afde9cfb1.png)
上面PLLSRC被置零后HSI2分频而PLLMUL被置为0000PLL2倍频输出，所以这里系统时钟频率就是HSI的频率。（HSI时钟频率为8MHz）
![![[Pasted image 20240717190444.png]]](https://i-blog.csdnimg.cn/direct/c3336098bfb54b8589a7a9bceb471aef.png)
reset这些为位应该是为了后面的配置系统时钟作准备。
后面的预处理指令都不会被处理知道 SetSysClock 函数，跳转到定义：
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
source (default after reset) */
}
![![[Pasted image 20240717191116.png]]](https://i-blog.csdnimg.cn/direct/a14b6c13af8347d68bc67cbac1dbc066.png)
在上面的图片中我们可以看到 SYSCLK_FREQ_72MHz 宏定义被放开了，也就是说固件库默认配置系统时钟为72MHz。
然后就会调用 SetSysClockTo72 函数将系统时钟配置为72MHz。
源码在这，不方便的同志们可以直接看下面的源码：
#elif defined SYSCLK_FREQ_72MHz
/**
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#endif
执行完 SetSysClock(); 函数 SystemInit 函数也就执行完成，接着就会跳转到main函数去执行用户编写的应用程序。
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