常见触发器、边沿检测电路的verilog实现

带同步复位端的D触发器

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
 
    always@(posedge clk)begin
        if(reset)begin
            q <= 8'd0;
        end
        else begin
            q <= d;
        end
    end
    
endmodule

带异步复位的D触发器

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
); 
    
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            q <= 8'd0;
        end
        else begin
            q <= d;
        end
    end
endmodule

带保持功能的D触发器

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
 
    always@(posedge clk)begin
        if(L)begin
            Q <= R;
        end
        else begin
            if(E)begin
                Q <= w;
            end
            else begin
                Q <= Q;
            end
        end
    end
 
endmodule

JK触发器

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always@(posedge clk)begin
        case({j, k})
            2'b00:begin
                Q <= Q;
            end
            2'b01:begin
                Q <= 1'b0;
            end
            2'b10:begin
                Q <= 1'b1;
            end
            2'b11:begin
                Q <= ~Q;
            end
        endcase
    end
 
endmodule

上升沿检测 电路

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]	in_reg;
    always@(posedge clk)begin
        in_reg <= in;  // 记忆上升沿来临前的信号
    end
  
    always@(posedge clk)begin
        pedge <= in & ~in_reg; //上升沿检测逻辑式
    end
    endmodule
    

双沿检测电路

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    
    reg [7:0]	in_reg;
    always@(posedge clk)begin
        in_reg <= in;
    end
    
    always@(posedge clk)begin
        anyedge = in ^ in_reg; // 双沿检测逻辑式
    end
 
endmodule

双边沿触发电路
对于双沿检测，一定不能使用always@(posedge clk or negedge clk)begin这种方式，这种方式是不可综合的

module top_module (
    input clk,
    input d,
    output q
);
    reg q_d1;
    reg q_d2;
    
    always@(posedge clk)begin
        q_d1 <= d ^ q_d2;
    end
    always@(negedge clk)begin
        q_d2 <= d ^ q_d1;
    end
    
    assign q = q_d1 ^ q_d2;
    
endmodule