1 Verilog语言要素
1.2 标识符-关键字-属性
1.2.1 标识符(Identifier)
规范原文如下:
- An identifier is used to give an object a unique name so it can be referenced.
- An identifier is either a simple identifier or an escaped identifier. – 转义标识符不常用
- A sample identifier shall be any sequence of letters, digits, dollar signs ($), and underscore characters (_).
- The first character of a simple identifier shall not be a digit or $; it can be a letter or an underscore.
- A name following the $ is interpreted as a system task or a system function.
- Identifiers shall be case sensitive.
个人总结如下: - 标识符(identifier)是由任意字母、数字和下划线(_)组成的字符序列;标识符的第一个字符必须是字母或者下划线;
- Verilog的标识符是大小写敏感的,即字符相同而大小写不同的两个标识符是不同的。
1.2.2 关键字(Keyword)
规范原文如下:
- Keywords are predefined nonescaped identifiers that are used to define the language constructs.
- A Verilog HDL keyword preceded by an escape character is not interpreted as a keyword.
- All keywords are defined in lowercase only.
个人总结如下: - 关键字是Verilog中预留的用于定义语言结构的特殊标识符,如assign、always等;
- Verilog中关键字不能大写;
- Verilog中关键字不能转义。
1.2.3 属性(Attribute)
规范原文如下:
- Attributes are used to control the operation or behavior of tools . – 控制仿真工具或开发工具的操作/行为
- An attribute_instance can appear in the Verilog description as a prefix attached to a declaration, a module item, a statement, or a port connection. – 可以是前缀
- It can appear as a suffix to an operator or a Verilog function name in an expression. – 可以是后缀
- If a value is not specifically assigned to the attribute, then its value shall be 1.
- Nesting of attribute instances is disallowed. – 不允许嵌套
语法格式如下:
规范举例如下:
例1:The following example shows how to attach attributes to a case statement.!
例2:To attach an attribute to a module definition.
例3:To attach an attribute to a module instantiation.
例4:To attach an attribute to a reg declaration.
例5:To attach an attribute to an operator. – 后缀
例6:To attach an attribute to a Verilog function call. – 后缀
例7:To attach an attribute to a conditional operator. – 后缀