ProASIC3 A3P060功能和应用分析

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JTAG

VPUMP和VJTAG的作用，

时钟

Figure 4-1 provides a simplified block diagram of the physical implementation of the building blocks in
each of the CCCs.

Hardwired I/O refers to global input pins that are hardwired to the multiplexer tree, which directly
accesses the CCC global buffers. These global input pins have designated pin locations and are
indicated with the I/O naming convention Gmn (m refers to any one of the positions where the PLL core
is available, and n refers to any one of the three global input MUXes and the pin number of the
associated global location, m). Choosing this option provides the benefit of directly connecting to the
CCC reference clock input, which provides less delay. See Figure 4-9 on page 76 for an example
illustration of the connections, shown in red. If a CLKDLY macro is initiated to utilize the programmable
delay element of the CCC, the clock input can be placed at one of nine dedicated global input pin
locations. In other words, if Hardwired I/O is chosen as the input source, the user can decide to place the
input pin in one of the GmA0, GmA1, GmA2, GmB0, GmB1, GmB2, GmC0, GmC1, or GmC2 locations of
the low power flash devices. When a PLL macro is used to utilize the PLL core in a CCC location, the
clock input of the PLL can only be connected to one of three GmA* global pin locations: GmA0, GmA1, or
GmA2.
可以看到A3P060只有GFA0/1/2三个脚，因为F位置有PLL，其余都是9个脚的输入

Figure 4-9 • Illustration of Hardwired I/O (global input pins) Usage for IGLOO and ProASIC3 devices 60 k Gates
and Larger

Table 4-5 • Number of CCCs by Device Size and Package

Figure 4-14 • CCC Locations in IGLOO and ProASIC3 Family Devices (except 10 k through 30 k gate devices)
10 k through 30 k gate devices do not support PLL features. In these devices, there are two CCC-GLs at
the lower corners (one at the lower right, and one at the lower left). These CCC-GLs do not have
programmable delays.
A3P030只有GEn和GDn

PLL

A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, or
CLKC-GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its reference clock. It uses
the GLA and, optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can
also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the
YB (or YC) output is used. Refer to the “PLL Macro Signal Descriptions” section on page 70 for more
information.
Each global buffer, as well as the PLL reference clock, can be driven from one of the following:
• 3 dedicated single-ended I/Os using a hardwired connection
• 2 dedicated differential I/Os using a hardwired connection (not supported for IGLOO nano or
ProASIC3 nano devices)
• The FPGA core
PLL使用CLKA，那CLKA怎么来呢？后面说了，专用IO或者FPGA core。
Clock Sources for PLL and CLKDLY Macros
The input reference clock (CLKA for a PLL macro, CLK for a CLKDLY macro) can be accessed from
different sources via the associated clock multiplexer tree. Each CCC has the option of choosing the
source of the input clock from one of the following:
• Hardwired I/O
• External I/O
• Core Logic
• RC Oscillator (Fusion only)
• Crystal Oscillator (Fusion only)
The SmartGen macro builder tool allows users to easily create the PLL and CLKDLY macros with the
desired settings. Microsemi strongly recommends using SmartGen to generate the CCC macros.
Hardwired I/O Clock Source
Hardwired I/O refers to global input pins that are hardwired to the multiplexer tree, which directly
accesses the CCC global buffers. These global input pins have designated pin locations and are
indicated with the I/O naming convention Gmn (m refers to any one of the positions where the PLL core
is available, and n refers to any one of the three global input MUXes and the pin number of the
associated global location, m). Choosing this option provides the benefit of directly connecting to the
CCC reference clock input, which provides less delay. See Figure 4-9 on page 76 for an example
illustration of the connections, shown in red. If a CLKDLY macro is initiated to utilize the programmable
delay element of the CCC, the clock input can be placed at one of nine dedicated global input pin
locations. In other words, if Hardwired I/O is chosen as the input source, the user can decide to place the
input pin in one of the GmA0, GmA1, GmA2, GmB0, GmB1, GmB2, GmC0, GmC1, or GmC2 locations of
the low power flash devices. When a PLL macro is used to utilize the PLL core in a CCC location, the
clock input of the PLL can only be connected to one of three GmA global pin locations: GmA0, GmA1, or
GmA2*.