verilog
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Verilog经典题
1.快时钟到慢时钟 检测单时钟脉冲信号2.跨时钟与3.同步复位异步释放4.任意小数分频5.状态机 Mealy Moore原创 2022-04-01 18:11:45 · 2793 阅读 · 0 评论 -
verilog(三) HDLBits
文章目录CircuitsSequential LogicFSMSimple one-hot state transitions 3*********5.3CircuitsSequential LogicFSMSimple one-hot state transitions 3module top_module( input in, input [3:0] state, output [3:0] next_state, output out); // .原创 2021-05-03 11:23:19 · 33 阅读 · 0 评论 -
verilog(二) HDLBits
文章目录CircuitsCombinational LogicMultiplexersMux256to1vArithmetic Circuitsxxx adder3-bit binary adderAdderSigned addition overflow4-digit BCD adderKarnaugh Map to Circuit3-variableCircuitsCombinational LogicMultiplexers4.14****************************.原创 2021-04-14 18:55:51 · 191 阅读 · 0 评论