verilog(三) HDLBits

---

---

*********5.3

Circuits

Sequential Logic

FSM

Simple one-hot state transitions 3

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = state[A]&~in | state[C]&~in;
    assign next_state[B] = in & (state[A] | state[B] | state[D]) ;
    assign next_state[C] = ~in & (state[B] | state[D] );
    assign next_state[D] = in & state[C];

    // Output logic: 
    assign out = (state[D]==1);

endmodule

Simple FSM 3(asynchronous reset )

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
	parameter A=0,B=1,C=2,D=3;//state
    reg [1:0] c_s,n_s;//current_state、next_state
    // State transition logic
    always@(*)
        case(c_s)
            A:begin
                if(in)
                    n_s = B;
                else
                    n_s = A;
            end
            B:begin
                if(in)
                    n_s = B;
                else
                    n_s = C;
            end
            C:begin
                if(in)
                    n_s = D;
                else
                    n_s = A;
            end
            D:begin
                if(in)
                    n_s = B;
                else
                    n_s = C;
            end
        endcase
    // State flip-flops with asynchronous reset
    always@(posedge clk, posedge areset)
        if(areset)
            c_s <= A;
    	else
            c_s <= n_s;
    

    // Output logic
	assign out = c_s==D;
endmodule

******5.24

Lemmings 1

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  
	parameter LEFT=0,RIGHT=1;
    // parameter LEFT=0, RIGHT=1, ...
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT: 
                begin
                    if(bump_left==1)
                        next_state = RIGHT;
                    else 
                        next_state = LEFT;
                    
                end
            RIGHT:
                begin
                    if(bump_right==1)
                        next_state = LEFT;
                    else 
                        next_state = RIGHT;
                    
                end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
         else 
             state <= next_state;
    end

    // Output logic
    // assign walk_left = (state == ...);
    // assign walk_right = (state == ...);
    assign {walk_left,walk_right} = {(state == LEFT),(state == RIGHT)};
    
	
endmodule

Lemmings 2