0简介
下面会介绍如何新建28377D的bios工程,重点注意cup1和cpu2的cmd的配置。
1新建bios工程
首先在D盘 新建文件夹 28377_bios_demo ,文件夹内 新建 c1_bios,c2_bios(存放project和应用程序) workspace(存放workspace) 。
上面文件夹结构属于个人习惯,主要可以避免较多工程时的管理成本,大家熟悉操作后可以按自己的习惯定义文件夹结构。
打开CCS ,在launcher 界面选择workspace文件夹路径。点击Launch。
同样方法新建C2_bios_demo
2 配置bios cfg
bios的cfg一些时钟配置还是需要的,CPU1和CPU2的 cfg基本一致,主要是在boot内的勾不勾选 initiate boot of the CPU2 processor
3 配置cmd
cmd与芯片的ram是对应的,这节不在这做过多解释直接上代码。
CPU1 cmd
/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== TMS320F28377D_C1.cmd ========
* Define the memory block start/length for the F28377D
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* BEGIN is used for the "boot to FLASH" bootloader mode */
D01SARAM : origin = 0x00B000, length = 0x001000
/* Flash boot address */
BEGIN : origin = 0x080000, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
// FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
// FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHEF : origin = 0x088000, length = 0x010000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1 : /* Data Memory */
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom
will use this for
stack */
M01SARAM : origin = 0x000122, length = 0x0006DE /* on-chip RAM */
LS05SARAM : origin = 0x008000, length = 0x003000 /* on-chip RAM */
/* on-chip Global shared RAMs */
//RAMGS0 : origin = 0x00C000, length = 0x001000
//RAMGS1 : origin = 0x00D000, length = 0x001000
//RAMGS2 : origin = 0x00E000, length = 0x001000
//RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS0_3 : origin = 0x00C000, length = 0x004000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
//RAMGS8 : origin = 0x014000, length = 0x001000
//RAMGS9 : origin = 0x015000, length = 0x001000
//RAMGS10 : origin = 0x016000, length = 0x001000
//RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS8_11 : origin = 0x014000, length = 0x004000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
/* Shared MessageRam */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
WAVE_DATA : origin = 0x0140000,length = 0x3FFFF
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
.binit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#ifdef __TI_EABI__
.init_array : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#else
.pinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#endif
.text : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
RUN = LS05SARAM PAGE = 1
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd)
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0,
RUN = LS05SARAM PAGE = 1,
table(BINIT)
#endif
#endif
/* Allocate uninitalized data sections: */
.stack : > M01SARAM | LS05SARAM PAGE = 1
.data : > M01SARAM | LS05SARAM PAGE = 1
#ifdef __TI_EABI__
.bss : > M01SARAM | LS05SARAM |RAMGS0_3 PAGE = 1
.sysmem : > LS05SARAM | M01SARAM PAGE = 1
#else
.ebss : > M01SARAM | LS05SARAM |RAMGS0_3 PAGE = 1
.esysmem : > LS05SARAM | M01SARAM PAGE = 1
#endif
.cio : > LS05SARAM | M01SARAM |RAMGS0_3 PAGE = 1
/* Initalized sections go in Flash */
#ifdef __TI_EABI__
.const : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#else
.econst : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#endif
.switch : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
.args : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
Filter_RegsFile : > RAMGS0_3 | RAMGS4 |
RAMGS5 | RAMGS6 | RAMGS7 | RAMGS8_11 | RAMGS12 | RAMGS13 | RAMGS14 |
RAMGS15 PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
WaveDataRam : > WAVE_DATA, PAGE = 1
/*User Data*/
ramgs5 : > RAMGS5, PAGE = 1
ramgs13 : > RAMGS13, PAGE = 1
/*Modbus Buf*/
ramgs6 : > RAMGS6, PAGE = 1
ramgs14 : > RAMGS14, PAGE = 1
/*Dma Buf*/
ramgs7 : > RAMGS7, PAGE = 1
ramgs15 : > RAMGS15, PAGE = 1
}
CPU2 cmd
/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== TMS320F28377D_C2.cmd ========
* Define the memory block start/length for the F28377D
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* BEGIN is used for the "boot to FLASH" bootloader mode */
D01SARAM : origin = 0x00B000, length = 0x001000
/* Flash boot address */
BEGIN : origin = 0x080000, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
// FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
// FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHEF : origin = 0x088000, length = 0x010000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1 : /* Data Memory */
BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom
will use this for
stack */
M01SARAM : origin = 0x000122, length = 0x0006DE /* on-chip RAM */
LS05SARAM : origin = 0x008000, length = 0x003000 /* on-chip RAM */
/* on-chip Global shared RAMs */
//RAMGS0 : origin = 0x00C000, length = 0x001000
//RAMGS1 : origin = 0x00D000, length = 0x001000
//RAMGS2 : origin = 0x00E000, length = 0x001000
//RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS0_3 : origin = 0x00C000, length = 0x004000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
//RAMGS8 : origin = 0x014000, length = 0x001000
//RAMGS9 : origin = 0x015000, length = 0x001000
//RAMGS10 : origin = 0x016000, length = 0x001000
//RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS8_11 : origin = 0x014000, length = 0x004000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
/* Shared MessageRam */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
WAVE_DATA : origin = 0x0140000,length = 0x40000
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
.binit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#ifdef __TI_EABI__
.init_array : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#else
.pinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#endif
.text : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
RUN = LS05SARAM PAGE = 1
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd)
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0,
RUN = LS05SARAM PAGE = 1,
table(BINIT)
#endif
#endif
/* Allocate uninitalized data sections: */
.stack : > M01SARAM | LS05SARAM PAGE = 1
.data : > M01SARAM | LS05SARAM PAGE = 1
#ifdef __TI_EABI__
.bss : > M01SARAM | LS05SARAM PAGE = 1
.sysmem : > LS05SARAM | M01SARAM PAGE = 1
#else
.ebss : > M01SARAM | LS05SARAM PAGE = 1
.esysmem : > LS05SARAM | M01SARAM PAGE = 1
#endif
.cio : > LS05SARAM | M01SARAM PAGE = 1
/* Initalized sections go in Flash */
#ifdef __TI_EABI__
.const : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#else
.econst : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
#endif
.switch : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
.args : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHEF |
FLASHG | FLASHH | FLASHI | FLASHJ |
FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
Filter_RegsFile : > RAMGS0_3 | RAMGS4 |
RAMGS5 | RAMGS6 | RAMGS7 | RAMGS8_11 | RAMGS12 | RAMGS13 | RAMGS14 |
RAMGS15 PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
WaveDataRam : > WAVE_DATA, PAGE = 1
/*User Data*/
ramgs5 : > RAMGS5, PAGE = 1
ramgs13 : > RAMGS13, PAGE = 1
/*Modbus Buf*/
ramgs6 : > RAMGS6, PAGE = 1
ramgs14 : > RAMGS14, PAGE = 1
/*Dma Buf*/
ramgs7 : > RAMGS7, PAGE = 1
ramgs15 : > RAMGS15, PAGE = 1
}
注意:第一次使用28377d经常出现cpu2 不能运行的情况 ,这种情况有个最常见的问题就是,shared Ram的配置不正确,一定注意shared Ram 是必须配置的,而且只能配置给cpu1 或cpu2(两者之一),在cmd 配置 ebss 、esysmem 注意配置到没有分配的shared Ram上。
包括对cla协控单元的配置也是一样的道理,所以一定对28377d ram的结构有所了解
void InitMemCfg(void)
{
EALLOW;
/*memory select*/
/*LS each 2K*16*/
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 0; //0---for cpu,1---for cla&cpu
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 0;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0; //0---for data,1---for program
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 0;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 0;
/*GS each 4K*16*/
//0---for cpu1,1---for cpu2
MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 0; //0x00C000
MemCfgRegs.GSxMSEL.bit.MSEL_GS1 = 0; //0x00D000
MemCfgRegs.GSxMSEL.bit.MSEL_GS2 = 0; //0x00E000
MemCfgRegs.GSxMSEL.bit.MSEL_GS3 = 0; //0x00F000
MemCfgRegs.GSxMSEL.bit.MSEL_GS4 = 0; //0x010000
MemCfgRegs.GSxMSEL.bit.MSEL_GS5 = 0; //0x011000
MemCfgRegs.GSxMSEL.bit.MSEL_GS6 = 0; //0x012000
MemCfgRegs.GSxMSEL.bit.MSEL_GS7 = 0; //0x013000
MemCfgRegs.GSxMSEL.bit.MSEL_GS8 = 1; //0x014000
MemCfgRegs.GSxMSEL.bit.MSEL_GS9 = 1; //0x015000
MemCfgRegs.GSxMSEL.bit.MSEL_GS10 = 1; //0x016000
MemCfgRegs.GSxMSEL.bit.MSEL_GS11 = 1; //0x017000
MemCfgRegs.GSxMSEL.bit.MSEL_GS12 = 1; //0x018000
MemCfgRegs.GSxMSEL.bit.MSEL_GS13 = 1; //0x019000
MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1; //0x01A000
MemCfgRegs.GSxMSEL.bit.MSEL_GS15 = 1; //0x01B000
EDIS;
}
配置完以上文件,基本上就可以添加驱动、初始化等等工作了,下次我会分享一下常用电力电子的dsp 基本软件架构。
另外欢迎来我这看看 http://www.sailingdeep.com/