ARM PTM, ETM和以物为师

于 2024-06-26 16:09:43 发布
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今早，一位同行通过微信发问：“幽兰的cpu支持arm ptm吗，就是那个类似于intel pt的功能。”

我当时正在忙，便做了一个简单回复：“用的rk3588，你自己查一下吧。”

对方回复了一个：行吧，加上一个捂脸的表情。

6f92476085dc84147124481e85a085fd.png

这个捂脸表情内涵丰富，多少带着点不满意。但对于这样的提问，如果去问苹果（Mac Book），问华为，问联想，问戴尔，我想多半也不会收到明确的回复。因为这是一个很深层的特征，是芯片内部的一个小众功能，是大多数人没听过的功能。即使对于专业的软件工程师或者硬件工程师，大多数人也是不知道的。

再退一步，这个技术源自ARM，但即使是问ARM的工程师，他们中的多数人也可能摇头。

再再退一步，这个技术应该出自某几个ARM的架构师以及工程师，即使是问他们，他们也可能会摇头，因为虽然他们亲自参加过这个技术的研发，但他们也未必清楚这个技术到底用在了哪一款笔记本，或者哪一款芯片上了。

ROM表里的报告

那么这个问题，应该问谁呢？

最快的方法是问“硬件”它自己。比如，使用挥码枪连接上幽兰后，开启NDB调试，输入!dap info，便得到一份详细而且精确的报告。

[ndb]!dap info
                AP ID register 0x24770002
                Type is MEM-AP APB2 or APB3
MEM-AP BASE 0x80000003
                Valid ROM table present
                Component base address 0x80000000
                Peripheral ID 0x0000080000
                Designer is 0x000, <invalid>
                Part is 0x000, Unrecognized
                Component class is 0x1, ROM table
                MEMTYPE system memory not present: dedicated debug bus
        ROMTABLE[0x0] = 0x01000003
                Component base address 0x81000000
                Peripheral ID 0x04007bb4e3
                Designer is 0x23b, ARM Ltd
                Part is 0x4e3, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x00, Miscellaneous, other
                Dev Arch is 0x47700af7, ARM Ltd "CoreSight ROM architecture" rev.0
                Type is ROM table
                MEMTYPE system memory not present: dedicated debug bus
        [L01] ROMTABLE[0x0] = 0x00001006
                Component not present
        [L01] ROMTABLE[0x4] = 0x00002006
                Component not present
        [L01] ROMTABLE[0x8] = 0x00004003
                Component base address 0x81004000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0xc] = 0x00005003
                Component base address 0x81005000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x10] = 0x00006003
                Component base address 0x81006000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x14] = 0x00007003
                Component base address 0x81007000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x18] = 0x00008002
                Component not present
        [L01] ROMTABLE[0x1c] = 0x00009002
                Component not present
        [L01] ROMTABLE[0x20] = 0x0000a002
                Component not present
        [L01] ROMTABLE[0x24] = 0x0000b002
                Component not present
        [L01] ROMTABLE[0x28] = 0x0000c003
                Component base address 0x8100c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x2c] = 0x0000d003
                Component base address 0x8100d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x30] = 0x0000e003
                Component base address 0x8100e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x34] = 0x0000f003
                Component base address 0x8100f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x38] = 0x00014003
                Component base address 0x81014000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x3c] = 0x00015003
                Component base address 0x81015000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x40] = 0x00016003
                Component base address 0x81016000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x44] = 0x00017003
                Component base address 0x81017000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x48] = 0x0001c003
                Component base address 0x8101c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x4c] = 0x0001d003
                Component base address 0x8101d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x50] = 0x0001e003
                Component base address 0x8101e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x54] = 0x0001f003
                Component base address 0x8101f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x58] = 0x00024003
                Component base address 0x81024000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x5c] = 0x00025003
                Component base address 0x81025000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x60] = 0x00026003
                Component base address 0x81026000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x64] = 0x00027003
                Component base address 0x81027000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x68] = 0x00028002
                Component not present
        [L01] ROMTABLE[0x6c] = 0x00029002
                Component not present
        [L01] ROMTABLE[0x70] = 0x0002a002
                Component not present
        [L01] ROMTABLE[0x74] = 0x0002b002
                Component not present
        [L01] ROMTABLE[0x78] = 0x0002c003
                Component base address 0x8102c000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x7c] = 0x0002d003
                Component base address 0x8102d000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x80] = 0x0002e003
                Component base address 0x8102e000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x84] = 0x0002f003
                Component base address 0x8102f000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x88] = 0x00034003
                Component base address 0x81034000
                Peripheral ID 0x04007bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x8c] = 0x00035003
                Component base address 0x81035000
                Peripheral ID 0x04007bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x90] = 0x00036003
                Component base address 0x81036000
                Peripheral ID 0x04007bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x94] = 0x00037003
                Component base address 0x81037000
                Peripheral ID 0x04007bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x98] = 0x0003c003
                Component base address 0x8103c000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x9c] = 0x0003d003
                Component base address 0x8103d000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0xa0] = 0x0003e003
                Component base address 0x8103e000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0xa4] = 0x0003f003
                Component base address 0x8103f000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0xa8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xac] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xbc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xcc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xdc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xec] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xfc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x100] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x104] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x108] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x10c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x110] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x114] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x118] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x11c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x120] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x124] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x128] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x12c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x130] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x134] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x138] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x13c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x140] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x144] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x148] = 0x00000000
        [L01]   End of ROM table
        ROMTABLE[0x4] = 0x00000000
                End of ROM table

上述报告来自RK3588芯片的ROM表。ROM是只读内存（Read Only Memory）的意思。ROM表是一种俗称，实质上就是指固化在芯片内部的技术参数。这些参数与芯片的设计绑定，一旦芯片测试完成，这些参数就固定了。

换句话来说，对于上面同行的问题，这个ROM表就是最好的老师，它比芯片设计者都更权威。因为芯片设计是海量工程，某个设计者也未必清楚表里的所有细节。

ETM和PTM

ROM表里的信息比较长，包含多方面的信息。对于同行的问题，密切相关的有四个表项，它们的信息大致相同，摘录其中之一如下：

[L01] ROMTABLE[0xa0] = 0x0003e003
                Component base address 0x8103e000
                Peripheral ID 0x04004bbd0b
                Designer is 0x23b, ARM Ltd
                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2

这个表项描述的是核景（CoreSight）技术的ETM部件。与同行问的PTM是同门兄弟。

根据ARM的官方资料，PTM和ETM都是ARM的处理器追踪技术（Processor Trace）。不同的处理器可能有不同的选择：PTM或者ETM。

ba4403e09cbfd7208ac6beda3ad0f59a.png

在同一篇白皮书里，ARM同行把PTM和ETM做了归纳。

99be409bb5407863355c384de2df26a5.png

但可惜的是，在上面这个归纳里，把PTM换了个名字，叫PFTv1，其实就是PTM。

在上图中的ETMv4描述中，ARM同行指出，ETM包含了PFTv1（PTM），如此看来，ETMv4是包含PTM的一个超集。

概而言之，PTM和ETM都是源自ARM的处理器追踪技术，它们的作用都是从微观意义的CPU那里获取执行状态信息（指令和数据），然后送给追踪端口或者追踪用的内存缓冲区。

5be0069a568291a014ed8d2b4a1192eb.png

二者比较，PTM技术很老了，技术文档里记录的版本都是在2008-2011年之间, 比较新的是ETMv4。

Revision History
Revision A11 April 2008First release for r0p0
Revision B31 December 2008First release for r1p0
Revision C08 July 2011Update for r1p0

https://developer.arm.com/documentation/ddi0401/c

ETM版本析疑

接下来的问题是，RK3588用的是哪种ETM呢？在上图中，有说包含ETMv4的微架构有Cortex-R7, Cortex-A53和Cortex-A57，没有提到3588使用A55和A76. 但是上面这个文档是2013年发表的，十年前的了，当时还没有A76.

还有个蹊跷的细节。在使用!dap info观察到的ROM表信息中，ETM的版本号里包含 rev.2, 没有写ETMv4.

ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2

这该如何解释呢？

我的推测时，2013年的文档就已经写ETMv4了，那么2020年设计的3588使用的就应该是ETMv4，但这是推测，需要证据。

对于ARM芯片的每一种微架构，ARM一般有一个TRM文档。

08df80eb95f74f55648132089feede70.png

打开A76的TRM，搜索ETMv4，果然有80多个命中。在A1.4中，找到支持我推测的有力证据：

df215a6be1ca39bcc2944a06b42019b3.png

3588使用A76支持ETMv4.2，也就是ETMv4，小版本号是0.2.

在ARM官方的A76的页面上，也可以找到同样的信息：

1560433c5a6b0e19dc73368903106b77.png

https://developer.arm.com/Processors/Cortex-A76

37d40b2b3f15d55f4141b4847dd0f7b0.png

顺便说一下，3588的4个小核是A55微架构，它也是支持ETMv4.2.

bdc7b689c3feda0c7036bd52da1d7000.png

https://developer.arm.com/Processors/Cortex-A55

结论和改进

看来，!dap info打印的是小版本号，而且在描述中没有明确写ETMv4。这是不是调试器代码的一个不足呢？

想到这里，我在调试器里运行ndb，开始我常做的DTD工作：debug the debugger。

先找到!dap info命令的实现，进入状态。

24654eb3bda285423ddc58aeffcb571e.png

再找到描述ETM的字符串。

static const struct {
  uint32_t arch_id;
  const char *description;
} class0x9_devarch[] = {
  /* keep same unsorted order as in ARM IHI0029E */
  { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
  { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
  { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
  { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
  { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
  { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
  { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
  { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
  { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
  { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
  { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
  { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
  { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
  { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
  { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
  { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
  { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
  { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
  { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
  { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
  { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
  { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
};

    ARM的核景技术博大精深，气势恢宏，杂而不乱。每个部件都有ID来标识。

    对于3588的ETM部件，调试器读到的ID为：0x47724a13

在A76 TRM的描述中，有这个寄存器的格式描述。

cc34aa8fa67e40e8b05912ff78d94e40.png

看来0x47724a13中2是小版本号，也就是rev.2的出处。低16位的0x4A13刚好和TRM中的描述一致。

更重要的是，在TRM中，对0x4A13的解释是ETMv4 component。这说明0x4A13这个ID就是代表ETMv4。

看来当前代码中的描述不够精确。于是，我调整代码，将0x4A13对应的描述从：

{ ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },

   修改为：

{ ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell architecture version 4 (ETMv4)" },

行尾加了条注释：// refined according to A76 TRM pg 542 

再次编译执行，!dap info显示出了更加精确的结果。

在今天这样信息大爆炸的时代里，很多技术的复杂度都翻倍演进，要把这些技术细节都放进人类大脑，那是不可能的了。所以，ARM这种把芯片参数记录在ROM表里的做法是非常科学的。有了ROM表机制后，当我们想要查找这个信息时，只要读一下这张表。前提是我们需要有这样一个硬件实物，这是我旅行时也总带着幽兰代码本的原因，我把这种方法称为“以物为师”。

写文章很辛苦，恳请各位读者点击“在看”，也欢迎转发）

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