Linux command --- lspci and setpci

1. lspci

it reads the information of the pci bus and device.

>sudo lspci -vvv

with parameter -vvv , it will show the device configure space and capabilities. For example:

Here is a bridge. First it has type1 configure space header as:

pci configure space type1 header

64:00.0 PCI bridge: Intel Corporation Sky Lake-E PCI Express Root Port 1A (rev 04) (prog-if 00 [Normal decode])
	Physical Slot: 6
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 30
	NUMA node: 0
	Bus: primary=64, secondary=65, subordinate=65, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: b6000000-b61fffff
	Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Subsystem: Intel Corporation Sky Lake-E PCI Express Root Port A
	Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
		Address: fee01000  Data: 4021
		Masking: 00000002  Pending: 00000000
	Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0
			ExtTag+ RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 256 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #5, Speed 8GT/s, Width x16, ASPM L1, Exit Latency L0s <512ns, L1 <16us
			ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
		LnkCtl:	ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 8GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #6, PowerLimit 0.000W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Off, PwrInd Off, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState+
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
		RootCap: CRSVisible+
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
		DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
		LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+
			 EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
	Capabilities: [e0] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3co
标题 Pre-emphasis apparatus, low voltage differential signaling transmitter including the same and pre-emphasis method Pre-emphasis apparatus, low voltage differential signaling transmitter including the same and pre-emphasis method Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine Voltage regulator for impedance matching and pre-emphasis, method of regulating voltage for impedance matching and pre-emphasis, voltage mode driver including the voltage regulator, and voltage-mode driver using the method Pre-emphasis circuit and differential current signaling system having the same Pre-emphasis circuit and differential current signaling system having the same Semiconductor device with output driver pre-emphasis scheme Pre-emphasis circuit Pre-emphasis automatic adjusting system, method of adjusting pre-emphasis and pre-emphasis setting signal generating circuit Distributed pre-emphasis equalizer Pre-emphasis automatic adjusting system, method of adjusting pre-emphasis and pre-emphasis setting signal generating circuit DAC based driver with selectable pre-emphasis signal levels DAC based driver with selectable pre-emphasis signal levels Method and apparatus for performing transmit pre-emphasis Differential Data Transmitter With Pre-Emphasis Method of half-bit pre-emphasis for multi-level signal Method of Half-Bit Pre-Emphasis for Multi-Level Signal DAC based driver with selectable pre-emphasis signal levels DAC based driver with selectable pre-emphasis signal levels Phase-adjusted pre-emphasis and equalization for data communication Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns Transmitters for loop-back adaptive pre-emphasis data transmission Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns Semiconductor memory device having pre-emphasis signal generator Method and apparatus for performing transmit pre-emphasis System and method of gen
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