spyglass DFT

SolvNet spyglass 

clock_11

内部 generated clocks 在shift mode 不被 testclock 控制。 

Fix

View the Incremental Schematic of the violation message. The Schematic Viewer window shows the flip-flop on which the clock does not reach. Ensure that the complete display mode is set.

Since the violation message provides information on identification of potential clocks, overlay (auxiliary violation mode) the Info_testmode rule and Info_testclock under shift_mode.

Double-click the Incremental Schematic to probe the fan-in code of the failing clock source. Identify the path on the basis of the signal name. The probed signal is annotated with the  <