2013年9月每日update

Update records for everyday

09/01/2013: 

Ran the simulation of top_bench.v in ModelSim SE 6.5b with RILL's code: E:\or1200-1.35\sim\rtl_sim\modelsim_sim, and got the 1st glimpse on the signal, blocks and architecture.

08/31/2013:

Went through the Neuro-Fuzzy logic mixed signal processor and plan to follow RBFNN (2013 ISCAS). 

And found there is a 16bit RISC in the digital controller so recalled the OpenRISC1200 as a good start point to learn RISC implementation on DE2 with different free soft-core IPs ( Xiang Li's 2011 MSEE thesis: they used 4 other IP: CONMAX IP Core; Memory Controller IP Core; UART16550 IP Core; GPIO IP Core)