library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;--导入程序中用到的库
entity readout is
port(
clk,rst_n:in std_logic;
clk100M:in std_logic;
ack,dck:in std_logic;
s1,s2,s3,s4,i1,i2,i3,i4,r1,r2,r3,r:out std_logic--实体部分,并定义好输入输出
);
end readout;
architecture one of readout is
signal cnt:std_logic_vector(15 downto 0);
type states is(read_line,read_idel,integretion);--声明三个状态类型,有多少个状态就声明几个状态类型
signal ack1:std_logic;
signal dck1:std_logic;
signal s1_read,s2_read,s3_read,s4_read,i1_read,i2_read,i3_read,i4_read:std_logic;
signal r1_read,r2_read,r3_read,r_read:std_logic;
signal pr_state,nx_state:states;--定义pr_state,nx_state状态属于states类型,一般是定义当前状态prsent_state与下一个状
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;--导入程序中用到的库
entity readout is
port(
clk,rst_n:in std_logic;
clk100M:in std_logic;
ack,dck:in std_logic;
s1,s2,s3,s4,i1,i2,i3,i4,r1,r2,r3,r:out std_logic--实体部分,并定义好输入输出
);
end readout;
architecture one of readout is
signal cnt:std_logic_vector(15 downto 0);
type states is(read_line,read_idel,integretion);--声明三个状态类型,有多少个状态就声明几个状态类型
signal ack1:std_logic;
signal dck1:std_logic;
signal s1_read,s2_read,s3_read,s4_read,i1_read,i2_read,i3_read,i4_read:std_logic;
signal r1_read,r2_read,r3_read,r_read:std_logic;
signal pr_state,nx_state:states;--定义pr_state,nx_state状态属于states类型,一般是定义当前状态prsent_state与下一个状