module zuoye(CLK,CNT,RST) ;
input CLK,RST;
output [ 3 : 0 ] CNT;
reg [ 3 : 0 ] CNT;
reg [3:0] max=4'd0110;
always @ (posedge CLK or posedge RST ) begin
if (RST) begin
CNT <=4'd0;
end
else begin
if (max<=9) begin
if (CNT<max) begin
CNT<=CNT+1'd1;
end
else begin
CNT<=0;
max=max+1'd1;
end
end
else begin
max<=6;
end
end
end
endmodule
计数器作业提交
最新推荐文章于 2021-01-17 13:59:12 发布