FPGA内部如果有无符号数转换

1.无符号数转化为有符号数

input  [9:0] DAT_ADC  ; 
output [9:0] DOUT     ; 
reg signed [9:0] DOUT  ; 
always @ (posedge CLK_ADC) begin  
DOUT    <= DAT_ADC - 2^a   ;
end

a为输入位宽

2.有符号数转化为无符号数

input  [12-1:0]  DATIN ;
output [12-1:0] DAT2DAC ;
reg [12-1:0]  DAT2DAC ;
reg [12-1:0]  datin_R1;
always @ (posedge CLKIN) begin
  datin_R1 [11: 0] <= {1'b1,DATIN[11:1]} - DATIN[11]*2^a;
  DAT2DAC          <= datin_R1 ;
end

a为输入位宽