modesim仿真错误解决

1、在添加Lattice ECP3的仿真库后，调用自身的serdes IP核联合modesim仿真时出现下列错误：

#         Region: /topblock_tf/UUT/I1
# ** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.
#    Time: 0 ns  Iteration: 0  Instance: /topblock_tf File: E:/code/FPGA_Mode2/FPGA_Mode2_tf.v
# FATAL ERROR while loading design
# Error loading design

貌似在说tf文件中的timscale与10fs不匹配，

将`timescale 10 ns / 1 ns改为=>`timescale 10 ns / 10 fs然后就好了