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Q3FSM--Exams/2014 q3fsm
module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z ); parameter A=0, B=1; reg state, next; always@(posedge clk)begin if(reset) state <= A; else原创 2021-03-15 14:05:16 · 569 阅读 · 0 评论 -
Exams/ece241 2014 q5a
module top_module ( input clk, input areset, input x, output z ); parameter [1:0] a=0, b=1, c=2; reg [2:0] state, next; always@(posedge clk or posedge areset)begin if(areset) state <= a; else state <= next; end always@(*)beg原创 2021-03-05 14:43:04 · 655 阅读 · 1 评论