Q3FSM--Exams/2014 q3fsm

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

    parameter A=0, B=1;
    reg state, next;
    
    always@(posedge clk)begin
        if(reset)
            state <= A;
        else
            state <= next;
    end
    
    always@(*)begin
        case(state)
            A: next = s ? B : A;
            B: begin
                next = B;
            end
            default: next = A;
        endcase
    end
    
    reg w1, w2;
    always@(posedge clk)begin
        if(reset)begin
            w1 <= 0;
            w2 <= 0;
        end
        else if( state == B )begin
            w1 <= w;
            w2 <= w1;
        end
        else begin
            w1 <= w1;
            w2 <= w2;
        end
    end
    
    always@(posedge clk)begin
        if(reset)begin
            z <= 0;
        end
        else if(counter==2'd0 && state == B) begin
            z <= (w1 | w2) & w;
        end
        else
            z <= 0;
    end
    
    reg [1:0] counter;
    always@(posedge clk)begin
        if(reset)
            counter <= 0;
        else if( next==B && counter <2'd2 )
            counter <= counter + 1;
        else if( next==B && counter == 2'd2 )
            counter <= 0;
        else
            counter <= 0;
    end
      
endmodule

这里作者的testbench貌似有点问题，附上仿真结果。看着也没啥毛病，嘻嘻。