Exams/ece241 2014 q5a

module top_module (
input clk,
input areset,
input x,
output z
);

parameter [1:0] a=0, b=1, c=2;
reg [2:0] state, next;

always@(posedge clk or posedge areset)begin
    if(areset)
        state <= a;
    else
        state <= next;
end

always@(*)begin
    case(state)
        a: next = x ? b : a;
        b: next = x ? c : b;
        c: next = x ? c : b;
    endcase
end

assign z = state == b;

endmodule