时钟实现任意占空比分频

1.实现偶数分频

module div_even(clk,outclk,rst);//占空比为50%
 input clk,rst;
 output outclk;
 reg outclk;
 reg [3:0] count;

 parameter N=4;//分频系数 N=输入时钟频率/输出时钟频率
 always @(posedge clk or posedge rst)
if(rst)
      begin outclk<=1'b0;
        count<=4'b0000;
      end
else
  begin
        if(count == N/2-1)//第N/2-1个上升沿到来时outclk翻转,计数器置零
	      begin outclk<=~outclk;
		        count<=4'b0000;
		  end
	   else
		  count<=count+1'b1;
  end
endmodule

module test;
 reg clk,rst;
 wire outclk;
 initial begin clk=1'b1;
               rst=1'b1;
			   #40 rst=~rst;
         end
 always #10 clk=~clk;
 div_even div_even(.clk(clk),.rst(rst),.outclk(outclk)); 
endmodule

二分频电路图：

 

四分频只需要复制电路就可以实现了！！ 

三分频电路：

 所示的译码复位电路，强制计数状态返回到初始全零状态，就是用NOR（或非门）门电路把Q2，Q1=“11B”的状态译码产生高电平复位脉冲，强迫FF1和FF2同时瞬间(在下一时钟输入Fi的脉冲到来之前)复零；

N=4   50%占空比

N=6  50%占空比

N=8  50%占空比

 偶分频实现任意占空比

module div_even(clk,outclk,rst);//4分频25%占空比
 input clk,rst;
 output outclk;
 reg outclk;
 reg [3:0] count;//计数
 parameter N=4;//分频系数 
 always @(posedge clk or posedge rst)
if(rst)
      begin outclk<=1'b1;
        count<=4'b0000;
      end
else
  begin
        if(count == 4'd0)//第1个上升沿到来时翻转,计数器加1
	      begin outclk<=~outclk;
		        count<=count+1'b1;
		  end
        else if(count == N-1)//第4个上升沿到来时outclk翻转,计数器置零
				      begin
					   outclk<=~outclk;
					   count<=4'd0;  
					  end
				  else//其他情况计数器加1
				      count<=count+1'b1; 
   end
endmodule

N=4 25%占空比

 N=4 75%占空比

N=6 16.7%占空比

 

 N=6 33%占空比

 N=6 50%占空比

N=6 66%占空比 

N=6 83%占空比  

2.实现奇数分频 

module divodd_renyi(clk,outclk,rst);
 input clk,rst;
 output outclk;
 reg outclk;
 reg [3:0] count;//计数
 parameter N=7;//分频系数 
 always @(posedge clk or posedge rst)
if(rst)
      begin outclk<=1'b0;
        count<=4'b0000;
      end
else
  begin
        if(count == 4'd2)//第0个上升沿到来时翻转,计数器加1 4/7的占空比
	      begin 
	              outclk<=~outclk;
		        count<=count+1'b1;
		  end
//        else if(count == 2)//第4个上升沿到来时outclk翻转,计数器置零
//            begin
//                    outclk<=~outclk;
//                    count<=count+1'b1;  
//              end
        else if(count == N-1)//第4个上升沿到来时outclk翻转,计数器置零
				      begin
					   outclk<=~outclk;
					   count<=4'd0;  
					  end
				  else//其他情况计数器加1
				      count<=count+1'b1; 
   end
endmodule

 N=7  4/7占空比

N=7  5/7占空比

 N=7  6/7占空比

  N=7  3/7占空比

 N=7  2/7占空比

 N=7  1/7占空比

3.奇数分频实现占空比为50%

module divodd50(clk,outclk,rst);
 input clk;
 input rst;
 output outclk;
 
 reg outclk1,outclk2;
 reg [3:0] count1,count2;
 parameter N=7;
 
 always @(posedge clk or posedge rst)//上升沿触发
   begin
        if(rst)
           begin
                count1 <= 4'd0;
                outclk1 <= 1'b0;
           end
        else
           begin
                if(count1 == 4'd2)
                    begin
                         outclk1 <= ~outclk1;
                         count1 <= count1 + 1'b1;
                    end
                else if(count1 == N-1)
                    begin
                         outclk1 <= ~outclk1;
                         count1 <= 4'd0;
                    end
                else
                    begin
                         count1 <= count1 + 1'b1;
                    end
           end
   end
   
   always @(negedge clk or posedge rst)//下降沿触发
      begin
           if(rst)
              begin
                   count2 <= 4'd0;
                   outclk2 <= 1'b0;
              end
           else
              begin
                   if(count2 == 4'd2)
                       begin
                            outclk2 <= ~outclk2;
                            count2 <= count2 + 1'b1;
                       end
                   else if(count2 == N-1)
                       begin
                            outclk2 <= ~outclk2;
                            count2 <= 4'd0;
                       end
                   else
                       begin
                            count2 <= count2 + 1'b1;
                       end
              end
      end
  assign outclk = outclk1 && outclk2;
endmodule

 N=7 占空比50%