testbench top是一个具有DUT和接口实例的静态容器(static container)。接口实例在TB top和DUT信号相连。生成时钟,并将初始重置适用于DUT。它/clock也被传递给接口句柄。接口使用set方法存储在uvm_config_db中,可以使用get方法沿层次结构向下检索。UVM testbench top还用于通过调用run_test()来触发测试。
Example of UVM Testbench Top for Adder design
`include "uvm_macros.svh"
import uvm_pkg::*;
module tb_top;
bit clk;
bit reset;
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
#5;
reset = 0;
end
add_if vif(clk, reset);
// Instantiate design top
adder DUT(.clk(vif.clk),
.reset(vif.reset),
.in1(vif.ip1),
.in2(vif.ip2),
.out(vif.out)
);
initial begin
// set interface in config_db
uvm_config_db#(virtual add_if)::set(uvm_root::get(), "*", "vif", vif);
// Dump waves
$dumpfile("dump.vcd");
$dumpvars;
end
initial begin
run_test("base_test");
end
endmodule
UVM Testbench Top with multiple agents