module vga_initials_top(
mclk,
btn,
sw,
hsync,
vsync,
red,
green,
blue
);
input wire mclk;
input wire btn;
input wire [7:0] sw;
output wire hsync;
output wire vsync;
output wire [2:0]red;
output wire [2:0]green;
output wire [1:0]blue;
wire clk,clk25,vidon;
wire [9:0] hc,vc;
wire [0:31]M;
wire [3:0] rom_addr4;
assign clr = btn;
clkdiv U1(
.mclk(mclk),
.clr(clr),
.clk25(clk25)
);
vga_640x480 U2(
.clk(clk25),
.clr(clr),
.hsync(hsync),
.vsync(vsync),
.hc(hc),
.vc(vc),
.vidon(vidon)
);
vga_initial U3(
.vidon(vidon),
.hc(hc),
.vc(vc),
.M(M),
.sw(sw),
.rom_addr4(rom_addr4),
.red(red),
.green(green),
.blue(blue)
);
prom_DMH U4(
.addr(rom_addr4),
.M(M)
);
endmodule
module clkdiv(
mclk,
clr,
clk25
);
input wire mclk;
input wire clr;
output wire clk25;
//output wire clk48;
reg [24:0] q;
always@(posedge mclk or posedge clr) begin
if(clr)
q <= 0;
else
q <= q + 1;
end
assign clk25 = q[1];
endmodule
module vga_640x480(
clk,
clr,
hsync,
vsync,
hc,
vc,
vidon
);
input wire clk;
input wire clr;
output reg hsync;
output reg vsync;
output reg [9:0] hc;
output reg [9:0] vc;
output reg vidon;
parameter hpixels = 10'b11001_00000; //琛屽儚绱犵偣=800
parameter vlines = 10'b10000_01001; //琛屾暟=521
parameter hbp = 10'b001000_10000;//
parameter hfp = 10'b11000_10000;
parameter vbp =10'b00000_11111;
parameter vfp = 10'b01111_11111;
reg vsensable; //enable for the vertical counter
//琛屽悓姝ヤ俊鍙疯鏁板櫒路
always@(posedge clk) begin
if(clr)
hc <= 0;
else
begin
if(hc == hpixels - 1) begin
hc <= 0;
vsensable <= 1;
//enable teh vertical counter to increase
end
else
begin
hc <= hc + 1;
vsensable <= 0; //leave the vsenable off
end
end
end
//浜х敓hsync鑴夊啿
//褰揾c涓~127鐨勬椂鍊欙紝琛屽悓姝ヤ俊鍙蜂负浣庣數骞
always@(*) begin
if(hc < 96)
hsync <= 0;
else
hsync <= 1;
end
//鍦哄悓姝ヤ俊鍙疯鏁板櫒
always@(posedge clk) begin
if(clr)
vc <= 0;
else begin
if(vsensable == 1) begin
if(vc &#