uclinux很久前笔记4

cpu/s3c44b0/start.s
_start:	b       reset
	ldr pc,=HandleUndef
	ldr pc,=HandleSWI
	ldr pc,=HandlePabort
	ldr pc,=HandleDabort
	b .
	ldr pc,=HandleIRQ
	ldr pc,=HandleFIQ
	ldr pc,=HandleEINT0 /*mGA H/W interrupt vector table*/
	ldr pc,=HandleEINT1
	ldr pc,=HandleEINT2
	ldr pc,=HandleEINT3
	ldr pc,=HandleEINT4567
	……
	b . /*mGKB*/
	b .
	b .
	.equ HandleReset, 0xc000000   //固定的将中断跳转到sdram中了
	.equ HandleUndef,0xc000004
	.equ HandleSWI, 0xc000008
	.equ HandlePabort, 0xc00000c
	.equ HandleDabort, 0xc000010
	.equ HandleReserved, 0xc000014
	.equ HandleIRQ, 0xc000018
	.equ HandleFIQ, 0xc00001c
	.equ HandleADC, 0xc000020
	.equ HandleRTC, 0xc000024
	.equ HandleUTXD1, 0xc000028
	.equ HandleUTXD0, 0xc00002c
……

	.balignl 16,0xdeadbeef
……
reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0x13
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */

#ifdef CONFIG_INIT_CRITICAL
	bl	cpu_init_crit
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a memsetup.S in your board directory.
	 */
	bl	memsetup			//初始化SDRAM
#endif

relocate:						/* relocate U-Boot to RAM	    */
	adr	r0, _start				/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1         	/* don't reloc during debug         */
	beq     stack_setup		//不等继续向下执行
// 其中TEXT_BASE=0x0C700000
	ldr	r2, _armboot_start    	//_armboot_start:  .word _start
	ldr	r3, _bss_start 			//此时的_armboot_start为链接地址中的_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:					
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp		r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop

/*
	now copy to sram the interrupt vector
*/
	adr	r0, real_vectors
	add	r2, r0, #1024
	ldr	r1, =0x0c000000 	//中断向量表重定位到0x0c000000地址处
	add	r1, r1, #0x08		//这里不明白为什么要加上0x08？？？
vector_copy_loop:
	ldmia	r0!, {r3-r10}
	stmia	r1!, {r3-r10}
	cmp	r0, r2
	ble	vector_copy_loop

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE				/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
	sub	r0, r0, #CFG_GBL_DATA_SIZE 	/* bdinfo                        */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12					/* leave 3 words for abort-stack    */
/********************************************************************
*		堆栈结构：
* 		_TEXT_BASE
* 		malloc area
* 		bdinfo
* 		CONFIG_STACKSIZE_IRQ
* 		CONFIG_STACKSIZE_FIQ
* 		#12
* 		SP
*********************************************************************/
	ldr	pc, _start_armboot	//跳转到c程序的start_armboot中(在/u-boot/lib_arm/board.c中)

_start_armboot:	.word start_armboot

/******************************************************************
* CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *********************************************************************/
#define INTCON (0x01c00000+0x200000)
#define INTMSK (0x01c00000+0x20000c)
#define LOCKTIME (0x01c00000+0x18000c)
#define PLLCON (0x01c00000+0x180000)
#define CLKCON (0x01c00000+0x180004)
#define WTCON (0x01c00000+0x130000)
#define BDIDES0 0x1f80008
#define BDIDES1 0x1f80028

cpu_init_crit:
	/* disable watch dog */
	ldr 	r0, =WTCON
	ldr	r1, =0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by clearing all bits in the INTMRs
	 */
	ldr	r1,=INTMSK
	ldr	r0, =0x03fffeff		
	str	r0, [r1]

	/* Set Clock Control Register */
	ldr	r1, =LOCKTIME
	ldrb	r0, =800
	strb	r0, [r1]

	ldr	r1, =PLLCON

#if CONFIG_S3C44B0_CLOCK_SPEED==60
   
	ldr	r0, =0x88042 /* 60MHz (Quartz=10MHz) */
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	ldr	r0, =0xac042  /* 75MHz  */
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif

	str	r0, [r1]

	ldr	r1,=CLKCON
	ldr	r0, =0x7ff8
	str	r0, [r1]
	
	ldr	r0, =BDIDES0       
	ldr	r1, =0x40000000  //BDIDESn reset value should be 0x40000000	 
	str	r1, [r0]

	ldr	r0, =BDIDES1      
	ldr	r1, =0x40000000   //BDIDESn reset value should be 0x40000000	 
	str	r1, [r0]
	
	mov	pc, lr

/*************************************************/
/*	interrupt vectors	*/
/*************************************************/
real_vectors:
	b	reset
	b	undefined_instruction
	b	software_interrupt
	b	prefetch_abort
	b	data_abort
	b	not_used
	b	irq
	b	fiq

/*************************************************/
undefined_instruction:
	mov	r6, #3
	b	reset
software_interrupt:
	mov	r6, #4
	b	reset
prefetch_abort:
	mov	r6, #5
	b	reset
data_abort:
	mov	r6, #6
	b	reset
not_used:
	/* we *should* never reach this */
	mov	r6, #7
	b	reset
irq:
	mov	r6, #8
	b	reset
fiq:
	mov	r6, #9
	b	reset