Clock Domain Crossing (CDC) Verification

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Clock Domain Crossing (CDC) Verification

by

Paul McLellan

Control signal synchronization


Data signal synchronization

When signals cross from one clock domain to another asynchronous domain, several problems can result: 

1. Metastability. When a signal from the first clock domain is transitioning just as the second clock domain is clocked, there may be an attempt to clock an invalid logic level into a register. The register may take some time to return to a stable state.
2. Convergence of separately synchronized signals. Since there are times when it is unclear whether a signal will be latched on one clock cycle or the subsequent on, it is possible that two signals changing simultaneously in one clock domain end up a cycle apart in the other domain.
3. Data loss when a signal crosses from a domain with a faster clock to one with a slower clock, for example. More positive synchronization such as handshaking may be necessary