Avalon-MM Clock Crossing Bridge

Avalon-MM Clock Crossing Bridge
The Avalon-MM Clock Crossing Bridge transfers Avalon-MM commands and responses between different
clock domains. You can also use the Avalon-MM Clock Crossing Bridge to bridge between AXI masters and
slaves of different clock domains.
The Avalon-MM Clock Crossing Bridge uses asynchronous FIFOs to implement the clock crossing logic.
The Clock Crossing Bridge has a number of parameters, including parameters to control the depth of the
command and response FIFOs in both the master and slave clock domains. If the number of in-flight reads
exceeds the depth of the response FIFO, the Clock Crossing Bridge stops sending reads. To maintain
throughput for high-performance applications, increase the response FIFO depth from the default minimum
depth, which is twice the maximum burst size